Hi,
On 06/03/18 15:58, Andre Przywara wrote:
Hi,
On 06/03/18 15:46, Julien Grall wrote:
Hi Andre,
On 05/03/18 16:03, Andre Przywara wrote:
The bit definition for the CPUID mask in the GICv2 LR register was
wrong, fortunately the current implementation does not use that bit.
Fix it up (it's s
Hi,
On 06/03/18 15:46, Julien Grall wrote:
> Hi Andre,
>
> On 05/03/18 16:03, Andre Przywara wrote:
>> The bit definition for the CPUID mask in the GICv2 LR register was
>> wrong, fortunately the current implementation does not use that bit.
>> Fix it up (it's starting at bit 10, not bit 9) and c
Hi Andre,
On 05/03/18 16:03, Andre Przywara wrote:
The bit definition for the CPUID mask in the GICv2 LR register was
wrong, fortunately the current implementation does not use that bit.
Fix it up (it's starting at bit 10, not bit 9) and clean up some
nearby definitions on the way.
This will be
The bit definition for the CPUID mask in the GICv2 LR register was
wrong, fortunately the current implementation does not use that bit.
Fix it up (it's starting at bit 10, not bit 9) and clean up some
nearby definitions on the way.
This will be used by the new VGIC shortly.
Signed-off-by: Andre Pr
