>>> On 26.04.19 at 12:22, wrote:
> Currently, configuration of the SYSENTER MSRs are behind a vendor check for
> Intel and Centaur, but this misses Zhaoxin.
>
> Use the feature bit, rather than a vendor check. cpu_has_sep is cleared early
> for AMD processors, which can't use SYSENTER/SYSEXIT wh
Currently, configuration of the SYSENTER MSRs are behind a vendor check for
Intel and Centaur, but this misses Zhaoxin.
Use the feature bit, rather than a vendor check. cpu_has_sep is cleared early
for AMD processors, which can't use SYSENTER/SYSEXIT when operating in long
mode.
Suggested-by: Ja
