On 05.09.2019 21:04, Andrew Cooper wrote:
> All 64-bit capable processors use PAT, and with PAT, it is explicitly
> permitted to have mappings with a cacheability different to MTRRs.
>
> On a native system with a real legacy VGA region, MTRRs will cause the region
> to be UC-.
Minor correction: M
On 06/09/2019 12:06, Roger Pau Monné wrote:
> On Thu, Sep 05, 2019 at 08:04:18PM +0100, Andrew Cooper wrote:
>> All 64-bit capable processors use PAT, and with PAT, it is explicitly
>> permitted to have mappings with a cacheability different to MTRRs.
>>
>> On a native system with a real legacy VGA
On Thu, Sep 05, 2019 at 08:04:18PM +0100, Andrew Cooper wrote:
> All 64-bit capable processors use PAT, and with PAT, it is explicitly
> permitted to have mappings with a cacheability different to MTRRs.
>
> On a native system with a real legacy VGA region, MTRRs will cause the region
> to be UC-.
All 64-bit capable processors use PAT, and with PAT, it is explicitly
permitted to have mappings with a cacheability different to MTRRs.
On a native system with a real legacy VGA region, MTRRs will cause the region
to be UC-. When booting virtualised, this range may be RAM and not a legacy
VGA re