Re: [XEN v5 07/11] xen/Arm: GICv3: Define ICH_LR_EL2 on AArch32

Hi Ayan, On 05/12/2022 13:26, Ayan Kumar Halder wrote: Refer "Arm IHI 0069H ID020922", 12.4.6, Interrupt Controller List Registers AArch64 System register ICH_LR_EL2 bits [31:0] are architecturally mapped to AArch32 System register ICH_LR[31:0]. AArch64 System register ICH_LR_EL2 bits [63:32] a

[XEN v5 07/11] xen/Arm: GICv3: Define ICH_LR_EL2 on AArch32

Refer "Arm IHI 0069H ID020922", 12.4.6, Interrupt Controller List Registers AArch64 System register ICH_LR_EL2 bits [31:0] are architecturally mapped to AArch32 System register ICH_LR[31:0]. AArch64 System register ICH_LR_EL2 bits [63:32] are architecturally mapped to AArch32 System register ICH_L