Hi Carlo,
On 20/02/2024 09:16, Carlo Nonato wrote:
Hi Julien
On Tue, Feb 20, 2024 at 12:06 AM Julien Grall wrote:
Hi,
On 14/02/2024 13:52, Carlo Nonato wrote:
On Wed, Feb 14, 2024 at 11:14 AM Michal Orzel wrote:
diff --git a/xen/arch/arm/include/asm/processor.h
b/xen/arch/arm/include/as
Hi Julien
On Tue, Feb 20, 2024 at 12:06 AM Julien Grall wrote:
>
> Hi,
>
> On 14/02/2024 13:52, Carlo Nonato wrote:
> > On Wed, Feb 14, 2024 at 11:14 AM Michal Orzel wrote:
> >>> diff --git a/xen/arch/arm/include/asm/processor.h
> >>> b/xen/arch/arm/include/asm/processor.h
> >>> index 8e0241046
Hi,
On 14/02/2024 13:52, Carlo Nonato wrote:
On Wed, Feb 14, 2024 at 11:14 AM Michal Orzel wrote:
diff --git a/xen/arch/arm/include/asm/processor.h
b/xen/arch/arm/include/asm/processor.h
index 8e02410465..336933ee62 100644
--- a/xen/arch/arm/include/asm/processor.h
+++ b/xen/arch/arm/include/
Hi Michal,
On Wed, Feb 14, 2024 at 11:14 AM Michal Orzel wrote:
>
> Hi Carlo,
>
> On 29/01/2024 18:17, Carlo Nonato wrote:
> >
> >
> > LLC coloring needs to know the last level cache layout in order to make the
> > best use of it. This can be probed by inspecting the CLIDR_EL1 register,
> > so th
Hi Carlo,
On 29/01/2024 18:17, Carlo Nonato wrote:
>
>
> LLC coloring needs to know the last level cache layout in order to make the
> best use of it. This can be probed by inspecting the CLIDR_EL1 register,
> so the Last Level is defined as the last level visible by this register.
> Note that t
LLC coloring needs to know the last level cache layout in order to make the
best use of it. This can be probed by inspecting the CLIDR_EL1 register,
so the Last Level is defined as the last level visible by this register.
Note that this excludes system caches in some platforms.
Static memory alloc
