> On 22 May 2023, at 10:30, Julien Grall wrote:
>
> Hi,
>
> On 22/05/2023 09:43, Luca Fancellu wrote:
>>> On 22 May 2023, at 08:50, Jan Beulich wrote:
>>>
>>> On 19.05.2023 16:46, Julien Grall wrote:
On 19/05/2023 15:26, Luca Fancellu wrote:
>> On 18 May 2023, at 10:35, Julien Grall
Hi,
On 22/05/2023 09:43, Luca Fancellu wrote:
On 22 May 2023, at 08:50, Jan Beulich wrote:
On 19.05.2023 16:46, Julien Grall wrote:
On 19/05/2023 15:26, Luca Fancellu wrote:
On 18 May 2023, at 10:35, Julien Grall wrote:
+/*
+ * Arm SVE feature code
+ *
+ * Copyright (C) 2022 ARM Ltd.
+ */
> On 22 May 2023, at 08:50, Jan Beulich wrote:
>
> On 19.05.2023 16:46, Julien Grall wrote:
>> On 19/05/2023 15:26, Luca Fancellu wrote:
On 18 May 2023, at 10:35, Julien Grall wrote:
> +/*
> + * Arm SVE feature code
> + *
> + * Copyright (C) 2022 ARM Ltd.
> + */
>
On 19.05.2023 16:46, Julien Grall wrote:
> On 19/05/2023 15:26, Luca Fancellu wrote:
>>> On 18 May 2023, at 10:35, Julien Grall wrote:
+/*
+ * Arm SVE feature code
+ *
+ * Copyright (C) 2022 ARM Ltd.
+ */
+
+#include
+#include
+#include
+#includ
Hi,
On 19/05/2023 16:13, Luca Fancellu wrote:
On 19/05/2023 15:51, Luca Fancellu wrote:
/* Control Registers */
/*
* CPTR_EL2 needs to be written before calling vfp_restore_state, a
* synchronization instruction is expected after the write (isb)
*/
WRITE_SYSREG(n->arch.cptr_el2, CPTR_EL2);
WRIT
> On 19 May 2023, at 16:00, Julien Grall wrote:
>
>
>
> On 19/05/2023 15:51, Luca Fancellu wrote:
>> /* Control Registers */
>> /*
>> * CPTR_EL2 needs to be written before calling vfp_restore_state, a
>> * synchronization instruction is expected after the write (isb)
>> */
>> WRITE_SYSREG(n-
On 19/05/2023 15:51, Luca Fancellu wrote:
/* Control Registers */
/*
* CPTR_EL2 needs to be written before calling vfp_restore_state, a
* synchronization instruction is expected after the write (isb)
*/
WRITE_SYSREG(n->arch.cptr_el2, CPTR_EL2);
WRITE_SYSREG(n->arch.cpacr, CPACR_EL1);
/*
* Thi
> On 19 May 2023, at 15:46, Julien Grall wrote:
>
> Hi Luca,
>
> On 19/05/2023 15:26, Luca Fancellu wrote:
>>> On 18 May 2023, at 10:35, Julien Grall wrote:
/*
* Comment from Linux:
* Userspace may perform DC ZVA instructions. Mismatched block sizes
diff --git a/xe
Hi Luca,
On 19/05/2023 15:26, Luca Fancellu wrote:
On 18 May 2023, at 10:35, Julien Grall wrote:
/*
* Comment from Linux:
* Userspace may perform DC ZVA instructions. Mismatched block sizes
diff --git a/xen/arch/arm/arm64/sve-asm.S b/xen/arch/arm/arm64/sve-asm.S
new file mode 100644
> On 18 May 2023, at 10:35, Julien Grall wrote:
>
> Hi Luca,
>
> Sorry for jumping late in the review.
Hi Julien,
Thank you for taking the time to review,
>>
>> /*
>>* Comment from Linux:
>>* Userspace may perform DC ZVA instructions. Mismatched block sizes
>> diff --git a/xen/ar
Hi Luca,
Sorry for jumping late in the review.
On 24/04/2023 07:02, Luca Fancellu wrote:
Enable Xen to handle the SVE extension, add code in cpufeature module
to handle ZCR SVE register, disable trapping SVE feature on system
boot only when SVE resources are accessed.
While there, correct codin
Enable Xen to handle the SVE extension, add code in cpufeature module
to handle ZCR SVE register, disable trapping SVE feature on system
boot only when SVE resources are accessed.
While there, correct coding style for the comment on coprocessor
trapping.
Now cptr_el2 is part of the domain context
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