Re: [PATCH v5 05/12] xen/arm: gicv3: implement handling of GICv3.1 eSPI

2025-09-03 Thread Leonid Komarianskyi
Hi Volodymyr, Thank tou for your review. On 29.08.25 22:55, Volodymyr Babchuk wrote: > > Hi Leonid, > > Leonid Komarianskyi writes: > >> Introduced appropriate register definitions, helper macros, >> and initialization of required GICv3.1 distributor registers >> to support eSPI. This type of

Re: [PATCH v5 05/12] xen/arm: gicv3: implement handling of GICv3.1 eSPI

2025-08-31 Thread Oleksandr Tyshchenko
On 29.08.25 19:06, Leonid Komarianskyi wrote: Hello Leonid Introduced appropriate register definitions, helper macros, and initialization of required GICv3.1 distributor registers to support eSPI. This type of interrupt is handled in the same way as regular SPI interrupts, with the followin

Re: [PATCH v5 05/12] xen/arm: gicv3: implement handling of GICv3.1 eSPI

2025-08-29 Thread Volodymyr Babchuk
Hi Leonid, Leonid Komarianskyi writes: > Introduced appropriate register definitions, helper macros, > and initialization of required GICv3.1 distributor registers > to support eSPI. This type of interrupt is handled in the > same way as regular SPI interrupts, with the following > differences

[PATCH v5 05/12] xen/arm: gicv3: implement handling of GICv3.1 eSPI

2025-08-29 Thread Leonid Komarianskyi
Introduced appropriate register definitions, helper macros, and initialization of required GICv3.1 distributor registers to support eSPI. This type of interrupt is handled in the same way as regular SPI interrupts, with the following differences: 1) eSPIs can have up to 1024 interrupts, starting f