Hi Bertand,
> -Original Message-
> From: Bertrand Marquis
> Sent: 2020年8月27日 22:13
> To: Wei Chen
> Cc: Xen-devel ; sstabell...@kernel.org;
> jul...@xen.org; Andre Przywara ; Penny Zheng
> ; Kaly Xin ; nd
> Subject: Re: [PATCH v4 2/2] xen/arm: Throw messag
Hi,
On 25/08/2020 17:06, Wei Chen wrote:
Arm ID_AA64PFR0_EL1 register provides two fields to describe CPU
FP/SIMD implementations. Currently, we exactly know the meaning of
0x0, 0x1 and 0xf of these fields. Xen treats value < 8 as FP/SIMD
features presented. If there is a value 0x2 bumped in the
> On 25 Aug 2020, at 17:06, Wei Chen wrote:
>
> Arm ID_AA64PFR0_EL1 register provides two fields to describe CPU
> FP/SIMD implementations. Currently, we exactly know the meaning of
> 0x0, 0x1 and 0xf of these fields. Xen treats value < 8 as FP/SIMD
> features presented. If there is a value 0x
Arm ID_AA64PFR0_EL1 register provides two fields to describe CPU
FP/SIMD implementations. Currently, we exactly know the meaning of
0x0, 0x1 and 0xf of these fields. Xen treats value < 8 as FP/SIMD
features presented. If there is a value 0x2 bumped in the future,
Xen behaviors for value <= 0x1 can
