Hi,
> On 30 Nov 2020, at 20:39, Volodymyr Babchuk
> wrote:
>
>
> Bertrand Marquis writes:
>
>> Add support for cp10 exceptions decoding to be able to emulate the
>> values for VMFR0 and VMFR1 when TID3 bit of HSR is activated.
>> This is required for aarch32 guests accessing VMFR0 and VMFR1 u
Bertrand Marquis writes:
> Add support for cp10 exceptions decoding to be able to emulate the
> values for VMFR0 and VMFR1 when TID3 bit of HSR is activated.
> This is required for aarch32 guests accessing VMFR0 and VMFR1 using vmrs
> and vmsr instructions.
is it VMFR or MVFR? According to the
Add support for cp10 exceptions decoding to be able to emulate the
values for VMFR0 and VMFR1 when TID3 bit of HSR is activated.
This is required for aarch32 guests accessing VMFR0 and VMFR1 using vmrs
and vmsr instructions.
Signed-off-by: Bertrand Marquis
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Changes in V2: rebase
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xen/arch/
