On Thu, May 15, 2025 at 08:47:46AM +0200, Jan Beulich wrote:
> On 14.05.2025 17:12, Roger Pau Monné wrote:
> > On Wed, May 14, 2025 at 03:20:56PM +0200, Jan Beulich wrote:
> >> On 14.05.2025 15:00, Roger Pau Monné wrote:
> >>> On Wed, May 03, 2023 at 11:47:18AM +0200, Jan Beulich wrote:
> Ther
On 14.05.2025 17:12, Roger Pau Monné wrote:
> On Wed, May 14, 2025 at 03:20:56PM +0200, Jan Beulich wrote:
>> On 14.05.2025 15:00, Roger Pau Monné wrote:
>>> On Wed, May 03, 2023 at 11:47:18AM +0200, Jan Beulich wrote:
There's no need to write back caches on all CPUs upon seeing a WBINVD
On Wed, May 14, 2025 at 03:20:56PM +0200, Jan Beulich wrote:
> On 14.05.2025 15:00, Roger Pau Monné wrote:
> > On Wed, May 03, 2023 at 11:47:18AM +0200, Jan Beulich wrote:
> >> There's no need to write back caches on all CPUs upon seeing a WBINVD
> >> exit; ones that a vCPU hasn't run on since the
On 14.05.2025 15:00, Roger Pau Monné wrote:
> On Wed, May 03, 2023 at 11:47:18AM +0200, Jan Beulich wrote:
>> There's no need to write back caches on all CPUs upon seeing a WBINVD
>> exit; ones that a vCPU hasn't run on since the last writeback (or since
>> it was started) can't hold data which may
On Wed, May 03, 2023 at 11:47:18AM +0200, Jan Beulich wrote:
> There's no need to write back caches on all CPUs upon seeing a WBINVD
> exit; ones that a vCPU hasn't run on since the last writeback (or since
> it was started) can't hold data which may need writing back.
Couldn't you do the same wit
There's no need to write back caches on all CPUs upon seeing a WBINVD
exit; ones that a vCPU hasn't run on since the last writeback (or since
it was started) can't hold data which may need writing back.
Signed-off-by: Jan Beulich
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With us not running AMD IOMMUs in non-coherent ways, I wonder w
