l...@kernel.org; Andre Przywara
>> ; Penny Zheng ; Kaly
>> Xin ; nd
>> Subject: Re: [PATCH v2 2/2] xen/arm: Throw messages for unknown
>> FP/SIMD implement ID
>>
>>
>>
>> On 24/08/2020 17:57, Bertrand Marquis wrote:
>>> Hi Julien,
>>
>
ATCH v2 2/2] xen/arm: Throw messages for unknown
> FP/SIMD implement ID
>
>
>
> On 24/08/2020 17:57, Bertrand Marquis wrote:
> > Hi Julien,
>
> Hi,
>
> >
> >> On 24 Aug 2020, at 14:34, Julien Grall wrote:
> >>
> >> Hi Wei,
>
On 24/08/2020 17:57, Bertrand Marquis wrote:
Hi Julien,
Hi,
On 24 Aug 2020, at 14:34, Julien Grall wrote:
Hi Wei,
On 24/08/2020 04:28, Wei Chen wrote:
Arm ID_AA64PFR0_EL1 register provides two fields to describe CPU
FP/SIMD implementations. Currently, we exactly know the meaning of
0
Hi Julien,
> On 24 Aug 2020, at 14:34, Julien Grall wrote:
>
> Hi Wei,
>
> On 24/08/2020 04:28, Wei Chen wrote:
>> Arm ID_AA64PFR0_EL1 register provides two fields to describe CPU
>> FP/SIMD implementations. Currently, we exactly know the meaning of
>> 0x0, 0x1 and 0xf of these fields. Xen trea
Hi Wei,
On 24/08/2020 04:28, Wei Chen wrote:
Arm ID_AA64PFR0_EL1 register provides two fields to describe CPU
FP/SIMD implementations. Currently, we exactly know the meaning of
0x0, 0x1 and 0xf of these fields. Xen treats value < 8 as FP/SIMD
features presented. If there is a value 0x2 bumped in
Hi,
> On 24 Aug 2020, at 04:28, Wei Chen wrote:
>
> Arm ID_AA64PFR0_EL1 register provides two fields to describe CPU
> FP/SIMD implementations. Currently, we exactly know the meaning of
> 0x0, 0x1 and 0xf of these fields. Xen treats value < 8 as FP/SIMD
> features presented. If there is a value
Arm ID_AA64PFR0_EL1 register provides two fields to describe CPU
FP/SIMD implementations. Currently, we exactly know the meaning of
0x0, 0x1 and 0xf of these fields. Xen treats value < 8 as FP/SIMD
features presented. If there is a value 0x2 bumped in the future,
Xen behaviors for value <= 0x1 can
