Re: [PATCH v2 2/2] x86/vlapic: Drop vlapic->esr_lock

On 05/03/2025 1:56 pm, Jan Beulich wrote: > On 03.03.2025 19:53, Andrew Cooper wrote: >> The exact behaviour of LVTERR interrupt generation is implementation >> specific. >> >> * Newer Intel CPUs generate an interrupt when pending_esr becomes >>nonzero. >> >> * Older Intel and all AMD CPUs ge

Re: [PATCH v2 2/2] x86/vlapic: Drop vlapic->esr_lock

On 03.03.2025 19:53, Andrew Cooper wrote: > The exact behaviour of LVTERR interrupt generation is implementation > specific. > > * Newer Intel CPUs generate an interrupt when pending_esr becomes >nonzero. > > * Older Intel and all AMD CPUs generate an interrupt when any >individual bit

[PATCH v2 2/2] x86/vlapic: Drop vlapic->esr_lock

The exact behaviour of LVTERR interrupt generation is implementation specific. * Newer Intel CPUs generate an interrupt when pending_esr becomes nonzero. * Older Intel and all AMD CPUs generate an interrupt when any individual bit in pending_esr becomes nonzero. Neither vendor documents