Re: [PATCH v10 9/9] x86emul: support FXSAVE/FXRSTOR

On 25/05/2020 15:30, Jan Beulich wrote: > Note that FPU selector handling as well as MXCSR mask saving for now > does not honor differences between host and guest visible featuresets. > > While for Intel operation of the insns with CR4.OSFXSR=0 is > implementation dependent, use the easiest solutio

[PATCH v10 9/9] x86emul: support FXSAVE/FXRSTOR

Note that FPU selector handling as well as MXCSR mask saving for now does not honor differences between host and guest visible featuresets. While for Intel operation of the insns with CR4.OSFXSR=0 is implementation dependent, use the easiest solution there: Simply don't look at the bit in the firs