Re: [PATCH 4/4] x86/vmx: Virtualize architectural LBRs

2024-11-26 Thread Jan Beulich
On 18.11.2024 09:49, ngoc-tu.d...@vates.tech wrote: > --- a/xen/arch/x86/cpu-policy.c > +++ b/xen/arch/x86/cpu-policy.c > @@ -788,6 +788,9 @@ static void __init calculate_hvm_max_policy(void) > > if ( !cpu_has_vmx_xsaves ) > __clear_bit(X86_FEATURE_XSAVES, fs); > + > +

[PATCH 4/4] x86/vmx: Virtualize architectural LBRs

2024-11-18 Thread ngoc-tu . dinh
From: Tu Dinh Virtual architectural LBRs work in guest mode only, using the "load guest IA32_LBR_CTL" and "clear IA32_LBR_CTL" VMX controls. Intercept writes to MSR_IA32_LASTBRANCH_{CTL,DEPTH} to inject LBR MSRs into guest. MSR_IA32_LASTBRANCH_DEPTH is only allowed to be equal to that of the hos