On Tue, Nov 14, 2023 at 02:44:09PM +, Andrew Cooper wrote:
> On 14/11/2023 2:11 pm, Roger Pau Monné wrote:
> > On Tue, Nov 14, 2023 at 12:55:46PM +, Andrew Cooper wrote:
> >> On 14/11/2023 12:32 pm, Jan Beulich wrote:
> >>> On 14.11.2023 13:18, Alejandro Vallejo wrote:
> On Tue, Nov 14
On 14/11/2023 2:11 pm, Roger Pau Monné wrote:
> On Tue, Nov 14, 2023 at 12:55:46PM +, Andrew Cooper wrote:
>> On 14/11/2023 12:32 pm, Jan Beulich wrote:
>>> On 14.11.2023 13:18, Alejandro Vallejo wrote:
On Tue, Nov 14, 2023 at 11:14:22AM +0100, Jan Beulich wrote:
> On 13.11.2023 18:53,
Hi,
On Tue, Nov 14, 2023 at 03:11:28PM +0100, Roger Pau Monné wrote:
> On Tue, Nov 14, 2023 at 12:55:46PM +, Andrew Cooper wrote:
> > On 14/11/2023 12:32 pm, Jan Beulich wrote:
> > > On 14.11.2023 13:18, Alejandro Vallejo wrote:
> > >> On Tue, Nov 14, 2023 at 11:14:22AM +0100, Jan Beulich wrot
On Tue, Nov 14, 2023 at 12:55:46PM +, Andrew Cooper wrote:
> On 14/11/2023 12:32 pm, Jan Beulich wrote:
> > On 14.11.2023 13:18, Alejandro Vallejo wrote:
> >> On Tue, Nov 14, 2023 at 11:14:22AM +0100, Jan Beulich wrote:
> >>> On 13.11.2023 18:53, Roger Pau Monné wrote:
> On Mon, Nov 13, 20
On 14/11/2023 12:32 pm, Jan Beulich wrote:
> On 14.11.2023 13:18, Alejandro Vallejo wrote:
>> On Tue, Nov 14, 2023 at 11:14:22AM +0100, Jan Beulich wrote:
>>> On 13.11.2023 18:53, Roger Pau Monné wrote:
On Mon, Nov 13, 2023 at 04:50:23PM +, Alejandro Vallejo wrote:
> Both Intel and AMD
On 14.11.2023 13:18, Alejandro Vallejo wrote:
> On Tue, Nov 14, 2023 at 11:14:22AM +0100, Jan Beulich wrote:
>> On 13.11.2023 18:53, Roger Pau Monné wrote:
>>> On Mon, Nov 13, 2023 at 04:50:23PM +, Alejandro Vallejo wrote:
Both Intel and AMD manuals agree that on x2APIC mode, the APIC LDR
On Tue, Nov 14, 2023 at 11:14:22AM +0100, Jan Beulich wrote:
> On 13.11.2023 18:53, Roger Pau Monné wrote:
> > On Mon, Nov 13, 2023 at 04:50:23PM +, Alejandro Vallejo wrote:
> >> Both Intel and AMD manuals agree that on x2APIC mode, the APIC LDR and ID
> >> registers are derivable from each oth
On Mon, Nov 13, 2023 at 06:53:00PM +0100, Roger Pau Monné wrote:
> On Mon, Nov 13, 2023 at 04:50:23PM +, Alejandro Vallejo wrote:
> > Both Intel and AMD manuals agree that on x2APIC mode, the APIC LDR and ID
> > registers are derivable from each other through a fixed formula.
> >
> > Xen uses
On 14/11/2023 10:14 am, Jan Beulich wrote:
> On 13.11.2023 18:53, Roger Pau Monné wrote:
>> On Mon, Nov 13, 2023 at 04:50:23PM +, Alejandro Vallejo wrote:
>>> Signed-off-by: Alejandro Vallejo
>> I do wonder whether we need to take any precautions with guests being
>> able to trigger an APIC re
On 13.11.2023 18:53, Roger Pau Monné wrote:
> On Mon, Nov 13, 2023 at 04:50:23PM +, Alejandro Vallejo wrote:
>> Both Intel and AMD manuals agree that on x2APIC mode, the APIC LDR and ID
>> registers are derivable from each other through a fixed formula.
>>
>> Xen uses that formula, but applies
On Mon, Nov 13, 2023 at 04:50:23PM +, Alejandro Vallejo wrote:
> Both Intel and AMD manuals agree that on x2APIC mode, the APIC LDR and ID
> registers are derivable from each other through a fixed formula.
>
> Xen uses that formula, but applies it to vCPU IDs (which are sequential)
> rather th
Both Intel and AMD manuals agree that on x2APIC mode, the APIC LDR and ID
registers are derivable from each other through a fixed formula.
Xen uses that formula, but applies it to vCPU IDs (which are sequential)
rather than x2APIC_IDs (which are not, at the moment). As I understand it,
this is an
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