Re: [PATCH] x86/svm: Use flush-by-asid when available

2020-05-07 Thread Jan Beulich
On 05.05.2020 20:25, Andrew Cooper wrote: > AMD Fam15h processors introduced the flush-by-asid feature, for more fine > grain flushing purposes. > > Flushing everything including ASID 0 (i.e. Xen context) is an an unnecesserily > large hammer, and never necessary in the context of guest TLBs needi

Re: [PATCH] x86/svm: Use flush-by-asid when available

2020-05-06 Thread Andrew Cooper
On 06/05/2020 08:08, Roger Pau Monné wrote: > On Tue, May 05, 2020 at 07:25:39PM +0100, Andrew Cooper wrote: >> AMD Fam15h processors introduced the flush-by-asid feature, for more fine >> grain flushing purposes. >> >> Flushing everything including ASID 0 (i.e. Xen context) is an an >> unnecesser

Re: [PATCH] x86/svm: Use flush-by-asid when available

2020-05-06 Thread Roger Pau Monné
On Tue, May 05, 2020 at 07:25:39PM +0100, Andrew Cooper wrote: > AMD Fam15h processors introduced the flush-by-asid feature, for more fine > grain flushing purposes. > > Flushing everything including ASID 0 (i.e. Xen context) is an an unnecesserily > large hammer, and never necessary in the contex

[PATCH] x86/svm: Use flush-by-asid when available

2020-05-05 Thread Andrew Cooper
AMD Fam15h processors introduced the flush-by-asid feature, for more fine grain flushing purposes. Flushing everything including ASID 0 (i.e. Xen context) is an an unnecesserily large hammer, and never necessary in the context of guest TLBs needing invalidating. When available, use TLB_CTRL_FLUSH