Re: [PATCH] x86/msr: fix handling of MSR_IA32_PERF_{STATUS/CTL}

2020-11-09 Thread Roger Pau Monné
Ping? On Thu, Oct 15, 2020 at 03:34:12PM +0200, Roger Pau Monné wrote: > On Wed, Oct 07, 2020 at 06:41:17PM +0200, Roger Pau Monné wrote: > > On Wed, Oct 07, 2020 at 01:06:08PM +0100, Andrew Cooper wrote: > > > On 06/10/2020 17:23, Roger Pau Monne wrote: > > > > Currently a PV hardware domain can

Re: [PATCH] x86/msr: fix handling of MSR_IA32_PERF_{STATUS/CTL}

2020-10-15 Thread Roger Pau Monné
On Wed, Oct 07, 2020 at 06:41:17PM +0200, Roger Pau Monné wrote: > On Wed, Oct 07, 2020 at 01:06:08PM +0100, Andrew Cooper wrote: > > On 06/10/2020 17:23, Roger Pau Monne wrote: > > > Currently a PV hardware domain can also be given control over the CPU > > > frequency, and such guest is allowed to

Re: [PATCH] x86/msr: fix handling of MSR_IA32_PERF_{STATUS/CTL}

2020-10-13 Thread Jan Beulich
On 06.10.2020 18:23, Roger Pau Monne wrote: > Currently a PV hardware domain can also be given control over the CPU > frequency, and such guest is allowed to write to MSR_IA32_PERF_CTL. > However since commit 322ec7c89f6 the default behavior has been changed > to reject accesses to not explicitly h

Re: [PATCH] x86/msr: fix handling of MSR_IA32_PERF_{STATUS/CTL}

2020-10-13 Thread Jan Beulich
On 07.10.2020 18:41, Roger Pau Monné wrote: > On Wed, Oct 07, 2020 at 01:06:08PM +0100, Andrew Cooper wrote: >> On 06/10/2020 17:23, Roger Pau Monne wrote: >>> Currently a PV hardware domain can also be given control over the CPU >>> frequency, and such guest is allowed to write to MSR_IA32_PERF_CT

Re: [PATCH] x86/msr: fix handling of MSR_IA32_PERF_{STATUS/CTL}

2020-10-07 Thread Roger Pau Monné
On Wed, Oct 07, 2020 at 01:06:08PM +0100, Andrew Cooper wrote: > On 06/10/2020 17:23, Roger Pau Monne wrote: > > Currently a PV hardware domain can also be given control over the CPU > > frequency, and such guest is allowed to write to MSR_IA32_PERF_CTL. > > This might be how the current logic "wo

Re: [PATCH] x86/msr: fix handling of MSR_IA32_PERF_{STATUS/CTL}

2020-10-07 Thread Andrew Cooper
On 06/10/2020 17:23, Roger Pau Monne wrote: > Currently a PV hardware domain can also be given control over the CPU > frequency, and such guest is allowed to write to MSR_IA32_PERF_CTL. This might be how the current logic "works", but its straight up broken. PERF_CTL is thread scope, so unless do

[PATCH] x86/msr: fix handling of MSR_IA32_PERF_{STATUS/CTL}

2020-10-06 Thread Roger Pau Monne
Currently a PV hardware domain can also be given control over the CPU frequency, and such guest is allowed to write to MSR_IA32_PERF_CTL. However since commit 322ec7c89f6 the default behavior has been changed to reject accesses to not explicitly handled MSRs, preventing PV guests that manage CPU fr