On 12.04.2021 13:39, Andrew Cooper wrote:
> On 12/04/2021 11:48, Jan Beulich wrote:
>> On 12.04.2021 12:22, Andrew Cooper wrote:
>>> --- a/xen/arch/x86/cpuid.c
>>> +++ b/xen/arch/x86/cpuid.c
>>> @@ -456,6 +456,12 @@ static void __init calculate_hvm_max_policy(void)
>>> __set_bit(X86_FEATURE_X2
On 12/04/2021 11:48, Jan Beulich wrote:
> On 12.04.2021 12:22, Andrew Cooper wrote:
>> --- a/xen/arch/x86/cpuid.c
>> +++ b/xen/arch/x86/cpuid.c
>> @@ -456,6 +456,12 @@ static void __init calculate_hvm_max_policy(void)
>> __set_bit(X86_FEATURE_X2APIC, hvm_featureset);
>>
>> /*
>> + *
On 12.04.2021 12:22, Andrew Cooper wrote:
> --- a/xen/arch/x86/cpuid.c
> +++ b/xen/arch/x86/cpuid.c
> @@ -456,6 +456,12 @@ static void __init calculate_hvm_max_policy(void)
> __set_bit(X86_FEATURE_X2APIC, hvm_featureset);
>
> /*
> + * We don't support EFER.LMSLE at all. AMD has dro
While part of the original AMD64 spec, Long Mode Segment Limit Enable was a
feature not picked up by Intel, and therefore didn't see much adoption in
software. AMD have finally dropped the feature from hardware, and allocated a
CPUID bit to indicate its absence.
Xen has never supported the featur
