ned-off-by: Xin Li (Intel)
---
Change in v1A:
*) Drop setting err to 0 in xen_do_read_msr() initially and set err to
0 in all callers (Jürgen Groß).
---
arch/x86/xen/enlighten_pv.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/x86/xen/enlighten_pv.c b/ar
ed-by: Dan Carpenter
Closes: https://lore.kernel.org/xen-devel/aBxNI_Q0-MhtBSZG@stanley.mountain/
Signed-off-by: Xin Li (Intel)
---
arch/x86/xen/enlighten_pv.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/x86/xen/enlighten_pv.c b/arch/x86/xen/enlighten_
The following commit:
efef7f184f2e ("x86/msr: Add explicit includes of ")
added a superfluous inclusion of to
drivers/acpi/processor_throttling.c.
Remove it.
Signed-off-by: Xin Li (Intel)
---
drivers/acpi/processor_throttling.c | 1 -
1 file changed, 1 deletion(-)
diff --git
Convert a native_wrmsr() use to native_wrmsrq() to zap meaningless type
conversions when a u64 MSR value is splitted into two u32.
Signed-off-by: Xin Li (Intel)
---
arch/x86/coco/sev/core.c | 7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/arch/x86/coco/sev/core.c b/arch
ange the function type of
native_read_msr_safe()").
3) Convert a native_wrmsr() use to native_wrmsrq() in
arch/x86/coco/sev/core.c.
Xin Li (Intel) (3):
x86/msr: Remove a superfluous inclusion of
x86/xen/msr: Fix uninitialized symbol 'err'
x86/msr: Convert a native_wrmsr() us
: Xin Li (Intel)
Acked-by: Dave Hansen
Acked-by: Peter Zijlstra (Intel)
Acked-by: Ilpo Järvinen
---
Change in v4A:
*) Use "git grep -l -e $PATTERN | grep -v -f <(git grep -l -e 'asm/msr\.h')"
to ensure ALL required *direct* inclusion of (Ilpo Järvinen).
Change in v4:
: Xin Li (Intel)
Acked-by: Dave Hansen
Acked-by: Peter Zijlstra (Intel)
---
Change in v4:
*) Add missing includes in a different patch (Ilpo Järvinen).
*) Add all necessary direct inclusions for msr.h (Ilpo Järvinen).
Change in v3:
* Add a problem statement to the changelog (Dave Hansen
For some reason, there are some TSC-related functions in the MSR
header even though there is a tsc.h header.
Relocate rdtsc{,_ordered}() from to , and
subsequently remove the inclusion of in .
Signed-off-by: Xin Li (Intel)
Acked-by: Dave Hansen
Acked-by: Peter Zijlstra (Intel)
---
Change
() is directly used when it needs to return an MSR
value in a u64 integer.
Add the native_rdmsrq() helper, which is simply an alias of __rdmsr(),
to make native_rdmsr() and native_rdmsrq() a pair of MSR read APIs.
Signed-off-by: Xin Li (Intel)
Acked-by: Peter Zijlstra (Intel)
---
Change in v2
hile at it, convert the data type of MSR index to u32 in functions
called in pmu_msr_chk_emulated().
Suggested-by: H. Peter Anvin (Intel)
Suggested-by: Juergen Gross
Signed-off-by: Xin Li (Intel)
Reviewed-by: Juergen Gross
Acked-by: Peter Zijlstra (Intel)
---
Change in v4:
*) Remove two &quo
rdpmc() is not used anywhere, remove it.
Signed-off-by: Xin Li (Intel)
Acked-by: Dave Hansen
Acked-by: Peter Zijlstra (Intel)
---
arch/x86/include/asm/msr.h | 7 ---
arch/x86/include/asm/paravirt.h | 7 ---
2 files changed, 14 deletions(-)
diff --git a/arch/x86/include/asm/msr.h
Now that rdpmc() is gone, i.e. rdpmcl() is the sole PMC read helper,
simply rename rdpmcl() to rdpmc().
Signed-off-by: Xin Li (Intel)
Acked-by: Dave Hansen
Acked-by: Peter Zijlstra (Intel)
---
Changes in v3:
*) Explain the reason of the renaming in the changelog (Dave Hansen).
*) Use shorter
ve the way for improving MSR API names, convert __rdmsr()
uses to native_rdmsrq() to ensure consistent usage. Later, these
APIs can be renamed to better reflect their implications, such as
native or pvops, with or without trace, and safe or non-safe.
No functional change intended.
Signed-off-by:
1-...@zytor.com/
This patch series is based on:
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git x86/msr
Xin Li (Intel) (15):
x86/msr: Add missing includes of
x86/msr: Move rdtsc{,_ordered}() to
x86/msr: Remove rdpmc()
x86/msr: Rename rdpmcl() to rdpmc()
x86/msr: Convert the rdp
The pv_ops PMC read API is defined as:
u64 (*read_pmc)(int counter);
But Xen PMC read functions return unsigned long long, make them
return u64 consistently.
Signed-off-by: Xin Li (Intel)
Reviewed-by: Juergen Gross
Acked-by: Peter Zijlstra (Intel)
---
arch/x86/xen/pmu.c | 6
safe APIs.
Remove the error pointer argument.
Signed-off-by: Xin Li (Intel)
Reviewed-by: Juergen Gross
Acked-by: Peter Zijlstra (Intel)
---
Change in v3:
*) Fix a typo: set_reg() => set_seg() (Juergen Gross).
---
arch/x86/xen/enlighten_pv.c | 16 +---
1 file changed, 5 inserti
, refactor pv_cpu_ops.write_msr{_safe}() to accept an MSR value
in a single u64 argument, replacing the current dual u32 arguments.
No functional change intended.
Signed-off-by: Xin Li (Intel)
Reviewed-by: Juergen Gross
Acked-by: Peter Zijlstra (Intel)
---
Change in v2:
* Spell out the reason why use a
way.
While at it, convert leftover MSR data type "unsigned int" to u32.
Signed-off-by: Xin Li (Intel)
Acked-by: Peter Zijlstra (Intel)
---
arch/x86/include/asm/msr.h| 21 +++--
arch/x86/include/asm/paravirt.h | 19 ---
arch/x86/i
native_write_msr{,_safe}(), which
has now been removed.
[1]:
https://lore.kernel.org/lkml/0ec48b84-d158-47c6-b14c-3563fd14b...@zytor.com/
Suggested-by: H. Peter Anvin (Intel)
Sign-off-by: Xin Li (Intel)
Reviewed-by: Juergen Gross
Acked-by: Peter Zijlstra (Intel)
---
Change in v3:
*) Rename pmu_msr_{read
enamed to better reflect their implications,
such as native or pvops, with or without trace, and safe or
non-safe.
No functional change intended.
Signed-off-by: Xin Li (Intel)
Acked-by: Peter Zijlstra (Intel)
---
Change in v2:
* Use native_wrmsr() where natural [rmid_p, closid_p] high/lo para
The third argument in wrmsr(msr, low, 0) is unnecessary. Instead, use
wrmsrq(msr, low), which automatically sets the higher 32 bits of the
MSR value to 0.
Signed-off-by: Xin Li (Intel)
Acked-by: Peter Zijlstra (Intel)
---
arch/x86/hyperv/hv_apic.c | 6 +++---
arch/x86/include
the returned value, further enhancing
readability.
Signed-off-by: Xin Li (Intel)
Acked-by: Dave Hansen
Acked-by: Peter Zijlstra (Intel)
---
Change in v3:
*) Add a changelog even it's obvious (Dave Hansen).
---
arch/x86/events/amd/uncore.c | 2 +-
arch/x86/events/c
hile at it, convert the data type of MSR index to u32 in functions
called in pmu_msr_chk_emulated().
Suggested-by: H. Peter Anvin (Intel)
Suggested-by: Juergen Gross
Signed-off-by: Xin Li (Intel)
---
Change in v3:
*) Remove the "emul" argument of pmu_msr_chk_emulated() (Juergen Gross
-off-by: Xin Li (Intel)
Acked-by: Dave Hansen
---
Change in v3:
* Add a problem statement to the changelog (Dave Hansen).
---
arch/x86/events/msr.c | 3 +
arch/x86/events/perf_event.h | 1 +
arch/x86/events/probe.c | 2 +
arch/x86
The third argument in wrmsr(msr, low, 0) is unnecessary. Instead, use
wrmsrq(msr, low), which automatically sets the higher 32 bits of the
MSR value to 0.
Signed-off-by: Xin Li (Intel)
---
arch/x86/hyperv/hv_apic.c | 6 +++---
arch/x86/include/asm/apic.h | 2
Now that rdpmc() is gone, i.e. rdpmcl() is the sole PMC read helper,
simply rename rdpmcl() to rdpmc().
Signed-off-by: Xin Li (Intel)
Acked-by: Dave Hansen
---
Changes in v3:
*) Explain the reason of the renaming in the changelog (Dave Hansen).
*) Use shorter name rdpmc() instead of rdpmcq
, refactor pv_cpu_ops.write_msr{_safe}() to accept an MSR value
in a single u64 argument, replacing the current dual u32 arguments.
No functional change intended.
Signed-off-by: Xin Li (Intel)
Reviewed-by: Juergen Gross
---
Change in v2:
* Spell out the reason why use a single u64 argument to pass the
safe APIs.
Remove the error pointer argument.
Signed-off-by: Xin Li (Intel)
Reviewed-by: Juergen Gross
---
Change in v3:
*) Fix a typo: set_reg() => set_seg() (Juergen Gross).
---
arch/x86/xen/enlighten_pv.c | 16 +---
1 file changed, 5 insertions(+), 11 deletions(-)
diff --gi
native_write_msr{,_safe}(), which
has now been removed.
[1]:
https://lore.kernel.org/lkml/0ec48b84-d158-47c6-b14c-3563fd14b...@zytor.com/
Suggested-by: H. Peter Anvin (Intel)
Sign-off-by: Xin Li (Intel)
---
Change in v3:
*) Rename pmu_msr_{read,write}() to pmu_msr_{read,write}_emulated()
(Dapeng Mi
rdpmc() is not used anywhere, remove it.
Signed-off-by: Xin Li (Intel)
Acked-by: Dave Hansen
---
arch/x86/include/asm/msr.h | 7 ---
arch/x86/include/asm/paravirt.h | 7 ---
2 files changed, 14 deletions(-)
diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h
enamed to better reflect their implications,
such as native or pvops, with or without trace, and safe or
non-safe.
No functional change intended.
Signed-off-by: Xin Li (Intel)
---
Change in v2:
* Use native_wrmsr() where natural [rmid_p, closid_p] high/lo parameters
can be used, without the
way.
While at it, convert leftover MSR data type "unsigned int" to u32.
Signed-off-by: Xin Li (Intel)
---
arch/x86/include/asm/msr.h| 21 +++--
arch/x86/include/asm/paravirt.h | 19 ---
arch/x86/include/asm/paravirt_types.h | 6 +++---
linux/kernel/git/tip/tip.git x86/msr
Xin Li (Intel) (14):
x86/msr: Move rdtsc{,_ordered}() to
x86/msr: Remove rdpmc()
x86/msr: Rename rdpmcl() to rdpmc()
x86/msr: Convert the rdpmc() macro into an always inline function
x86/msr: Return u64 consistently in Xen PMC read functions
x8
ve the way for improving MSR API names, convert __rdmsr()
uses to native_rdmsrq() to ensure consistent usage. Later, these
APIs can be renamed to better reflect their implications, such as
native or pvops, with or without trace, and safe or non-safe.
No functional change intended.
Signed-off-by:
The pv_ops PMC read API is defined as:
u64 (*read_pmc)(int counter);
But Xen PMC read functions return unsigned long long, make them
return u64 consistently.
Signed-off-by: Xin Li (Intel)
Reviewed-by: Juergen Gross
---
arch/x86/xen/pmu.c | 6 +++---
arch/x86/xen/xen-ops.h | 2
the returned value, further enhancing
readability.
Signed-off-by: Xin Li (Intel)
Acked-by: Dave Hansen
---
Change in v3:
*) Add a changelog even it's obvious (Dave Hansen).
---
arch/x86/events/amd/uncore.c | 2 +-
arch/x86/events/core.c| 2 +-
arch/x86/e
() is directly used when it needs to return an MSR
value in a u64 integer.
Add the native_rdmsrq() helper, which is simply an alias of __rdmsr(),
to make native_rdmsr() and native_rdmsrq() a pair of MSR read APIs.
Signed-off-by: Xin Li (Intel)
---
Change in v2:
* Split into two changes and add the
rdpmc() is not used anywhere, remove it.
Signed-off-by: Xin Li (Intel)
---
arch/x86/include/asm/msr.h | 7 ---
arch/x86/include/asm/paravirt.h | 7 ---
2 files changed, 14 deletions(-)
diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h
index 2caa13830e11
native_rdmsrq() doesn't do trace thus can be used in noinstr context,
rename it to native_rdmsrq_no_trace() to make it explicit.
Signed-off-by: Xin Li (Intel)
---
arch/x86/boot/startup/sme.c | 4 ++--
arch/x86/events/amd/brs.c | 2 +-
arch/x86/hyperv/hv_
alternatives pattern, possibly invoking a
different exception handling pattern there, or at least indicating the
"real" location of the fault.
Signed-off-by: H. Peter Anvin (Intel)
Signed-off-by: Xin Li (Intel)
---
arch/x86/include/asm/asm.h | 6 +
arch/x86/include/a
Signed-off-by: Xin Li (Intel)
---
arch/x86/include/asm/msr.h | 4 ++--
arch/x86/kvm/svm/svm.c | 6 +++---
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h
index 72a1c3301d46..a1c63bed14be 100644
--- a/arch/x86/include/asm
native_rdmsr() doesn't do trace thus can be used in noinstr context,
rename it to native_rdmsr_no_trace() to make it explicit.
Signed-off-by: Xin Li (Intel)
---
arch/x86/include/asm/microcode.h | 2 +-
arch/x86/include/asm/msr.h| 8
arch/x86/kernel/cpu/microcode/
n handling
pattern there, or at least indicating the "real" location of the fault.
patches 21 and 22 refactor the code to use the alternatives mechanism to
read and write MSR.
Patches 23 ~ 34 are afterwards cleanups.
H. Peter Anvin (Intel) (1):
x86/extable: Implement EX_TYPE_FUNC_REWIND
Use native MSR API __native_{wr,rd}msrq() instead of MSR assemely.
Signed-off-by: Xin Li (Intel)
---
arch/x86/kernel/cpu/mce/core.c | 55 +-
1 file changed, 35 insertions(+), 20 deletions(-)
diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce
Convert native_rdmsr_no_trace() uses to native_rdmsrq_no_trace() uses
cleanly with the use of struct msr, and remove native_rdmsr_no_trace().
Signed-off-by: Xin Li (Intel)
---
arch/x86/include/asm/microcode.h | 6 +++---
arch/x86/include/asm/msr.h| 13 +++--
arch/x86
native_wrmsrq() doesn't do trace thus can be used in noinstr context,
rename it to native_wrmsrq_no_trace() to make it explicit.
Signed-off-by: Xin Li (Intel)
---
arch/x86/events/amd/brs.c | 2 +-
arch/x86/hyperv/ivm.c | 2 +-
arch/x86/include/asm/a
ism is also used to choose the new immediate
form MSR write instruction when it's available.
Consequently, remove the pv_ops MSR write APIs and the Xen callbacks.
[1]: https://lore.kernel.org/lkml/87y1h81ht4.ffs@tglx/
Originally-by: H. Peter Anvin (Intel)
Signed-off-by: Xin Li (Intel)
-
native_wrmsr() doesn't do trace thus can be used in noinstr context,
rename it to native_wrmsr_no_trace() to make it explicit.
Signed-off-by: Xin Li (Intel)
---
arch/x86/include/asm/msr.h| 8
arch/x86/kernel/cpu/resctrl/pseudo_lock.c | 4 ++--
2 files chang
Signed-off-by: Xin Li (Intel)
---
arch/x86/hyperv/ivm.c | 2 +-
arch/x86/include/asm/msr.h | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/x86/hyperv/ivm.c b/arch/x86/hyperv/ivm.c
index dfddf522e838..8860c6c0f013 100644
--- a/arch/x86/hyperv/ivm.c
+++ b/arch
Signed-off-by: Xin Li (Intel)
---
arch/x86/include/asm/msr.h | 4 ++--
arch/x86/kernel/kvmclock.c | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h
index 2a62a899f7a5..72a1c3301d46 100644
--- a/arch/x86/include/asm
Signed-off-by: Xin Li (Intel)
---
arch/x86/include/asm/msr.h | 4 ++--
arch/x86/kvm/svm/svm.c | 10 +-
arch/x86/xen/pmu.c | 4 ++--
3 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h
index 4c7aa9e7fbac
Since the ARGS macros are no longer used in the MSR read/write API
implementation, move them after their definitions.
Signed-off-by: Xin Li (Intel)
---
arch/x86/include/asm/msr.h | 38 +-
1 file changed, 21 insertions(+), 17 deletions(-)
diff --git a/arch
ed to change, but the approaches
how they perform MSR operations are binary patched during boot time upon
availability of MSR instructions.
Signed-off-by: Xin Li (Intel)
---
arch/x86/boot/startup/sme.c | 4 ++--
arch/x86/events/amd/brs.c | 2 +-
arch/x86/hyperv/hv_
Signed-off-by: Xin Li (Intel)
---
arch/x86/hyperv/hv_apic.c | 6 +++---
arch/x86/include/asm/apic.h | 2 +-
arch/x86/include/asm/switch_to.h | 2 +-
arch/x86/kernel/cpu/amd.c | 2 +-
arch/x86/kernel/cpu/common.c | 8
feature bit for MSR immediate form instructions.
Suggested-by: Borislav Petkov (AMD)
Signed-off-by: Xin Li (Intel)
---
arch/x86/include/asm/cpufeatures.h | 1 +
arch/x86/kernel/cpu/scattered.c| 1 +
2 files changed, 2 insertions(+)
diff --git a/arch/x86/include/asm/cpufeatures.h
b/arch/x86
Signed-off-by: Xin Li (Intel)
---
arch/x86/events/amd/uncore.c | 2 +-
arch/x86/events/core.c| 2 +-
arch/x86/events/intel/core.c | 4 ++--
arch/x86/events/intel/ds.c| 2 +-
arch/x86/include/asm/msr.h| 2 +-
arch
As pmu_msr_{read,write}() are now wrappers of pmu_msr_chk_emulated(),
remove them and use pmu_msr_chk_emulated() directly.
While at it, convert the data type of MSR index to u32 in functions
called in pmu_msr_chk_emulated().
Suggested-by: H. Peter Anvin (Intel)
Signed-off-by: Xin Li (Intel
Relocate rdtsc{,_ordered}() from to , and
subsequently remove the inclusion of in .
Consequently, must be included in several source files
that previously did not require it.
Signed-off-by: Xin Li (Intel)
---
arch/x86/boot/startup/sme.c | 1 +
arch/x86/events/msr.c
native_write_msr{,_safe}(), which
has now been removed.
[1]:
https://lore.kernel.org/lkml/0ec48b84-d158-47c6-b14c-3563fd14b...@zytor.com/
Suggested-by: H. Peter Anvin (Intel)
Sign-off-by: Xin Li (Intel)
---
arch/x86/xen/enlighten_pv.c | 6 +-
arch/x86/xen/pmu.c | 27
Signed-off-by: Xin Li (Intel)
---
arch/x86/events/amd/uncore.c | 2 +-
arch/x86/events/core.c| 2 +-
arch/x86/events/intel/core.c | 4 ++--
arch/x86/events/intel/ds.c| 2 +-
arch/x86/include/asm/msr.h| 5
, refactor pv_cpu_ops.write_msr{_safe}() to accept an MSR value
in a single u64 argument, replacing the current dual u32 arguments.
No functional change intended.
Signed-off-by: Xin Li (Intel)
---
Change in v2:
* Spell out the reason why use a single u64 argument to pass the MSR
value in the lowest
e Xen callbacks.
Suggested-by: H. Peter Anvin (Intel)
Signed-off-by: Xin Li (Intel)
---
arch/x86/include/asm/msr.h| 277 +++---
arch/x86/include/asm/paravirt.h | 40
arch/x86/include/asm/paravirt_types.h | 9 -
arch/x86/kernel/paravirt.c
ed to change, but the approaches
how they perform MSR operations are binary patched during boot time upon
availability of MSR instructions.
Signed-off-by: Xin Li (Intel)
---
Change in v2:
* Use native_wrmsr() where natural [rmid_p, closid_p] high/lo parameters
can be used, without the
Add the instruction opcodes used by the immediate form WRMSRNS/RDMSR
to x86-opcode-map.
Signed-off-by: Xin Li (Intel)
---
arch/x86/lib/x86-opcode-map.txt | 5 +++--
tools/arch/x86/lib/x86-opcode-map.txt | 5 +++--
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/arch/x86/lib
The MSR read APIs no longer expect RAX or EDX:EAX to be cleared upon
returning from #GP caused by MSR read instructions.
The MSR safe APIs no longer assume -EIO being returned in a register
from #GP caused by MSR instructions.
Remove new dead code due to above changes.
Signed-off-by: Xin Li
Change function type of native_read_msr_safe() to
int native_read_msr_safe(u32 msr, u64 *val)
to make it the same as the type of native_write_msr_safe().
Signed-off-by: Xin Li (Intel)
---
arch/x86/include/asm/msr.h| 21 +++--
arch/x86/include/asm
Signed-off-by: Xin Li (Intel)
---
arch/x86/include/asm/msr.h | 18 ++
arch/x86/mm/extable.c | 39 +-
2 files changed, 52 insertions(+), 5 deletions(-)
diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h
index c955339be9c9
Convert a native_wrmsr() use to native_wrmsrq() to zap meaningless type
conversions when a u64 MSR value is splitted into two u32.
Signed-off-by: Xin Li (Intel)
---
arch/x86/include/asm/sev-internal.h | 7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/arch/x86/include/asm
(X86_FEATURE_XENPV), the
kernel runtime binary is patched to unconditionally jump
to the Xen PMC read code.
Consequently, remove the pv_ops PMC read API.
Signed-off-by: Xin Li (Intel)
---
arch/x86/include/asm/msr.h| 31 ---
arch/x86/include
safe APIs.
Remove the error pointer argument.
Signed-off-by: Xin Li (Intel)
---
arch/x86/xen/enlighten_pv.c | 16 +---
1 file changed, 5 insertions(+), 11 deletions(-)
diff --git a/arch/x86/xen/enlighten_pv.c b/arch/x86/xen/enlighten_pv.c
index b5a8bceb5f56..9a89cb29fa35 100644
--- a
() is directly used when it needs to return an MSR
value in a u64 integer.
Add the native_rdmsrq() helper, which is simply an alias of __rdmsr(),
to make native_rdmsr() and native_rdmsrq() a pair of MSR read APIs.
Signed-off-by: Xin Li (Intel)
---
Change in v2:
* Split into two changes and add the
The pv_ops PMC read API is defined as:
u64 (*read_pmc)(int counter);
But Xen PMC read functions return unsigned long long, make them
return u64 consistently.
Signed-off-by: Xin Li (Intel)
---
arch/x86/xen/pmu.c | 6 +++---
arch/x86/xen/xen-ops.h | 2 +-
2 files changed, 4
Also add support for the immediate form MSR read support.
Suggested-by: H. Peter Anvin (Intel)
Signed-off-by: Xin Li (Intel)
---
arch/x86/include/asm/msr.h| 274 --
arch/x86/include/asm/paravirt.h | 40
arch/x86/include/asm/paravirt_types.h | 9
)
Sign-off-by: Xin Li (Intel)
---
arch/x86/xen/enlighten_pv.c | 6 +-
arch/x86/xen/pmu.c | 27 ---
arch/x86/xen/xen-ops.h | 4 ++--
3 files changed, 11 insertions(+), 26 deletions(-)
diff --git a/arch/x86/xen/enlighten_pv.c b/arch/x86/xen/enlighten_pv.c
EX_TYPE_FUNC_REWIND
Xin Li (Intel) (14):
x86/msr: Replace __wrmsr() with native_wrmsrl()
x86/msr: Replace __rdmsr() with native_rdmsrl()
x86/msr: Simplify pmu_msr_{read,write}()
x86/msr: Let pv_cpu_ops.write_msr{_safe}() take an u64 instead of two
u32
x86/msr: Replace wrmsr(msr, low, 0
Refactor pv_cpu_ops.write_msr{_safe}() to take the input MSR value
in a single u64 argument, replacing the current dual u32 arguments.
No functional change intended.
Signed-off-by: Xin Li (Intel)
---
arch/x86/include/asm/msr.h| 33 ---
arch/x86/include/asm
alternatives pattern, possibly invoking a
different exception handling pattern there, or at least indicating the
"real" location of the fault.
Signed-off-by: H. Peter Anvin (Intel)
Signed-off-by: Xin Li (Intel)
---
arch/x86/include/asm/asm.h | 6 +
arch/x86/include/a
Signed-off-by: Xin Li (Intel)
---
arch/x86/include/asm/msr-index.h | 6 ++
arch/x86/kvm/vmx/vmenter.S | 28
2 files changed, 30 insertions(+), 4 deletions(-)
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index
Signed-off-by: Xin Li (Intel)
---
arch/x86/hyperv/hv_apic.c | 6 +++---
arch/x86/include/asm/apic.h | 2 +-
arch/x86/include/asm/switch_to.h | 2 +-
arch/x86/kernel/cpu/amd.c | 2 +-
arch/x86/kernel/cpu/common.c | 8
Since the ARGS macros are no longer used in the MSR read/write API
implementation, move them after their definitions.
Signed-off-by: Xin Li (Intel)
---
arch/x86/include/asm/msr.h | 34 +-
1 file changed, 17 insertions(+), 17 deletions(-)
diff --git a/arch/x86
__wrmsr() is the lowest level primitive MSR write API, and its direct
use is NOT preferred. Use its wrapper function native_wrmsrl() instead.
No functional change intended.
Signed-off-by: Xin Li (Intel)
---
arch/x86/events/amd/brs.c | 2 +-
arch/x86/include/asm/apic.h
feature bit for MSR immediate form instructions.
Suggested-by: Borislav Petkov
Signed-off-by: Xin Li (Intel)
---
arch/x86/include/asm/cpufeatures.h | 19 ++-
arch/x86/kernel/cpu/scattered.c| 1 +
2 files changed, 11 insertions(+), 9 deletions(-)
diff --git a/arch/x86/include
Now pmu_msr_{read,write}() just do pmu_msr_chk_emulated(), so remove
them and call pmu_msr_chk_emulated() directly.
Suggested-by: H. Peter Anvin (Intel)
Signed-off-by: Xin Li (Intel)
---
arch/x86/xen/enlighten_pv.c | 17 ++---
arch/x86/xen/pmu.c | 24
Also add support for the immediate form MSR write support.
Originally-by: H. Peter Anvin (Intel)
Signed-off-by: Xin Li (Intel)
---
arch/x86/include/asm/fred.h | 2 +-
arch/x86/include/asm/msr.h| 340 ++
arch/x86/include/asm/paravirt.h | 22
__rdmsr() is the lowest level primitive MSR read API, and its direct
use is NOT preferred. Use its wrapper function native_rdmsrl() instead.
No functional change intended.
Signed-off-by: Xin Li (Intel)
---
arch/x86/coco/sev/core.c | 2 +-
arch/x86/events/amd/brs.c
Add the instruction opcodes used by the immediate form WRMSRNS/RDMSR
to x86-opcode-map.
Signed-off-by: Xin Li (Intel)
---
arch/x86/lib/x86-opcode-map.txt | 5 +++--
tools/arch/x86/lib/x86-opcode-map.txt | 5 +++--
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/arch/x86/lib
Signed-off-by: Xin Li (Intel)
---
arch/x86/include/asm/msr.h | 18 ++
1 file changed, 2 insertions(+), 16 deletions(-)
diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h
index 121597fc5d41..da4f2f6d127f 100644
--- a/arch/x86/include/asm/msr.h
+++ b/arch/x86
Signed-off-by: Xin Li (Intel)
---
arch/x86/mm/extable.c | 59 ++-
1 file changed, 41 insertions(+), 18 deletions(-)
diff --git a/arch/x86/mm/extable.c b/arch/x86/mm/extable.c
index eb9331240a88..56138c0762b7 100644
--- a/arch/x86/mm/extable.c
+++ b/arch
architectures are not affected because __{start,end}_init_task
are used on x86 only.
Reviewed-by: Juergen Gross
Signed-off-by: Xin Li (Intel)
---
Change since v2:
* Rebase to the latest tip master branch.
Change since v1:
* Revert an accident insane change, init_task to init_stack (Jürgen Groß
architectures are not affected because __{start,end}_init_task
are used on x86 only.
Signed-off-by: Xin Li (Intel)
---
Change since v1:
* Revert an accident insane change, init_task to init_stack (Jürgen Groß).
---
arch/x86/include/asm/processor.h | 4 ++--
arch/x86/kernel/head_64.S | 2
architectures are not affected because __{start,end}_init_task
are used on x86 only.
Signed-off-by: Xin Li (Intel)
---
arch/x86/include/asm/processor.h | 4 ++--
arch/x86/kernel/head_64.S | 2 +-
arch/x86/xen/xen-head.S | 2 +-
include/asm-generic/vmlinux.lds.h | 8
4
t;x86/fred: Reserve space for the FRED stack frame")
Fixes: 3adee777ad0d ("x86/smpboot: Remove initial_stack on 64-bit")
Reported-by: kernel test robot
Closes: https://lore.kernel.org/oe-lkp/202402262159.183c2a37-...@intel.com
Signed-off-by: Xin Li (Intel)
---
Change
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