On 6/11/2025 5:58 AM, Juergen Gross wrote:
Here is a patch I cooked. I added an ALTERNATIVE() hack because the
new instructions can't be more than 6 bytes long. But with the patch you
just sent, it shouldn't be needed.
I have meanwhile dropped the patch copying the original indirect call.
R
On 5/12/2025 1:45 AM, Xin Li (Intel) wrote:
Convert a native_wrmsr() use to native_wrmsrq() to zap meaningless type
conversions when a u64 MSR value is splitted into two u32.
Signed-off-by: Xin Li (Intel)
---
arch/x86/coco/sev/core.c | 7 +--
1 file changed, 1 insertion(+), 6 deletions
ned-off-by: Xin Li (Intel)
---
Change in v1A:
*) Drop setting err to 0 in xen_do_read_msr() initially and set err to
0 in all callers (Jürgen Groß).
---
arch/x86/xen/enlighten_pv.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/x86/xen/enlighten_pv.c b/ar
On 5/17/2025 6:21 AM, Ingo Molnar wrote:
Ah, indeed, it's also a startup code wrapper, which wrmsrq() doesn't
have at the moment. Fair enough.
So you want me to drop this patch then?
No, patch #3 is fine as-is in its -v1 form
Thanks for confirming.
I'll just update patch #2 as version v1A th
On 5/16/2025 6:42 AM, Jürgen Groß wrote:
On 15.05.25 20:11, Xin Li wrote:
On 5/15/2025 8:29 AM, Ingo Molnar wrote:
* Xin Li (Intel) wrote:
xen_read_msr_safe() currently passes an uninitialized argument err to
xen_do_read_msr(). But as xen_do_read_msr() may not set the argument
>>> On 5/15/2025 10:54 AM, Xin Li wrote:
>>> On 5/15/2025 8:27 AM, Ingo Molnar wrote:
>>>>
>>>> * Xin Li (Intel) wrote:
>>>>
>>>>> Convert a native_wrmsr() use to native_wrmsrq() to zap meaningless type
>>>>&
On 5/15/2025 10:54 AM, Xin Li wrote:
On 5/15/2025 8:27 AM, Ingo Molnar wrote:
* Xin Li (Intel) wrote:
Convert a native_wrmsr() use to native_wrmsrq() to zap meaningless type
conversions when a u64 MSR value is splitted into two u32.
BTW., at this point we should probably just replace
On 5/15/2025 8:29 AM, Ingo Molnar wrote:
* Xin Li (Intel) wrote:
xen_read_msr_safe() currently passes an uninitialized argument err to
xen_do_read_msr(). But as xen_do_read_msr() may not set the argument,
xen_read_msr_safe() could return err with an unpredictable value.
To ensure
On 5/15/2025 8:27 AM, Ingo Molnar wrote:
* Xin Li (Intel) wrote:
Convert a native_wrmsr() use to native_wrmsrq() to zap meaningless type
conversions when a u64 MSR value is splitted into two u32.
BTW., at this point we should probably just replace
sev_es_wr_ghcb_msr() calls with direct
On 5/13/2025 3:24 PM, H. Peter Anvin wrote:
On May 12, 2025 11:06:02 PM PDT, "Jürgen Groß" wrote:
On 13.05.25 07:55, Xin Li wrote:
On 5/12/2025 4:24 AM, Juergen Gross wrote:
Now with the mentioned patch really attached. :-)
Does it allow patching with an instruction more than 6
On 5/12/2025 4:20 AM, Jürgen Groß wrote:
On 09.05.25 10:18, Xin Li wrote:
On 5/6/2025 2:20 AM, Juergen Gross wrote:
I'm trying to evaluate how to add the immediate form MSR instructions
on top of this patch set. And I'm close to get it done.
There is something to consider when ru
On 5/12/2025 11:06 PM, Jürgen Groß wrote:
On 13.05.25 07:55, Xin Li wrote:
On 5/12/2025 4:24 AM, Juergen Gross wrote:
Now with the mentioned patch really attached. :-)
Does it allow patching with an instruction more than 6 bytes long?
The immediate form MSR instructions are 9 bytes long
On 5/12/2025 4:24 AM, Juergen Gross wrote:
Now with the mentioned patch really attached. :-)
Does it allow patching with an instruction more than 6 bytes long?
The immediate form MSR instructions are 9 bytes long.
Thanks!
Xin
ed-by: Dan Carpenter
Closes: https://lore.kernel.org/xen-devel/aBxNI_Q0-MhtBSZG@stanley.mountain/
Signed-off-by: Xin Li (Intel)
---
arch/x86/xen/enlighten_pv.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/x86/xen/enlighten_pv.c b/arch/x86/xen/enlighten_
The following commit:
efef7f184f2e ("x86/msr: Add explicit includes of ")
added a superfluous inclusion of to
drivers/acpi/processor_throttling.c.
Remove it.
Signed-off-by: Xin Li (Intel)
---
drivers/acpi/processor_throttling.c | 1 -
1 file changed, 1 deletion(-)
diff --git
Convert a native_wrmsr() use to native_wrmsrq() to zap meaningless type
conversions when a u64 MSR value is splitted into two u32.
Signed-off-by: Xin Li (Intel)
---
arch/x86/coco/sev/core.c | 7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/arch/x86/coco/sev/core.c b/arch
ange the function type of
native_read_msr_safe()").
3) Convert a native_wrmsr() use to native_wrmsrq() in
arch/x86/coco/sev/core.c.
Xin Li (Intel) (3):
x86/msr: Remove a superfluous inclusion of
x86/xen/msr: Fix uninitialized symbol 'err'
x86/msr: Convert a native_wrmsr() us
On 5/6/2025 2:20 AM, Juergen Gross wrote:
Instead of having callback functions for rdmsr/wrmsr on native, switch
to inline the respective instructions directly in order to avoid
overhead with the call interface.
To me, this is a beneficial addition to the existing pvops MSR code.
This requir
On 5/2/2025 1:02 AM, Ingo Molnar wrote:
* Xin Li (Intel) wrote:
index 94408a784c8e..13335a130edf 100644
--- a/arch/x86/include/asm/tsc.h
+++ b/arch/x86/include/asm/tsc.h
@@ -7,7 +7,81 @@
#include
#include
-#include
+
+/*
+ * both i386 and x86_64 returns 64-bit value in edx:eax
On 5/2/2025 1:18 AM, Ingo Molnar wrote:
* Xin Li (Intel) wrote:
For some reason, there are some TSC-related functions in the MSR
^^^
header even though there is a tsc.h header.
The real reason is that the rdtsc{,_ordered}() methods use the
EAX_EDX_*() macros to optimize
On 5/2/2025 1:52 AM, Ingo Molnar wrote:
* Xin Li (Intel) wrote:
For some reason, there are some TSC-related functions in the MSR
header even though there is a tsc.h header.
Relocate rdtsc{,_ordered}() from to , and
subsequently remove the inclusion of in .
Signed-off-by: Xin Li (Intel
On 5/2/2025 6:13 AM, Ilpo Järvinen wrote:
diff --git a/arch/x86/kernel/trace_clock.c b/arch/x86/kernel/trace_clock.c
index b8e7abe00b06..708d61743d15 100644
--- a/arch/x86/kernel/trace_clock.c
+++ b/arch/x86/kernel/trace_clock.c
@@ -4,7 +4,7 @@
*/
#include
#include
-#include
+#include
: Xin Li (Intel)
Acked-by: Dave Hansen
Acked-by: Peter Zijlstra (Intel)
Acked-by: Ilpo Järvinen
---
Change in v4A:
*) Use "git grep -l -e $PATTERN | grep -v -f <(git grep -l -e 'asm/msr\.h')"
to ensure ALL required *direct* inclusion of (Ilpo Järvinen).
Change in v4:
On 4/30/2025 2:17 AM, Ilpo Järvinen wrote:
While this is not my subsystem so don't have the final say here, you had
to explain quite much to prove that (and reviewer would have to go through
the same places to check). Wouldn't it be much simpler for all if all
those .c files would just include d
On 4/29/2025 9:20 PM, Michael Kelley wrote:
Also under hyperv/ not all files are covered but I'm a bit hesitant to
suggest a change there since I'm not sure if they (hypervisors) do
something special w.r.t. msr.
I've worked on the Hyper-V code in Linux for 8 years or so, first as
a Microsoft emp
On 4/29/2025 2:45 AM, Ilpo Järvinen wrote:
arch/x86/events/msr.c | 3 +++
arch/x86/events/perf_event.h | 1 +
arch/x86/events/probe.c | 2 ++
Under arch/x86/events/ a few files seem
On 4/29/2025 2:45 AM, Ilpo Järvinen wrote:
On Sun, 27 Apr 2025, Xin Li (Intel) wrote:
For some reason, there are some TSC-related functions in the MSR
header even though there is a tsc.h header.
To facilitate the relocation of rdtsc{,_ordered}() from
to and to eventually eliminate the
: Xin Li (Intel)
Acked-by: Dave Hansen
Acked-by: Peter Zijlstra (Intel)
---
Change in v4:
*) Add missing includes in a different patch (Ilpo Järvinen).
*) Add all necessary direct inclusions for msr.h (Ilpo Järvinen).
Change in v3:
* Add a problem statement to the changelog (Dave Hansen
For some reason, there are some TSC-related functions in the MSR
header even though there is a tsc.h header.
Relocate rdtsc{,_ordered}() from to , and
subsequently remove the inclusion of in .
Signed-off-by: Xin Li (Intel)
Acked-by: Dave Hansen
Acked-by: Peter Zijlstra (Intel)
---
Change
() is directly used when it needs to return an MSR
value in a u64 integer.
Add the native_rdmsrq() helper, which is simply an alias of __rdmsr(),
to make native_rdmsr() and native_rdmsrq() a pair of MSR read APIs.
Signed-off-by: Xin Li (Intel)
Acked-by: Peter Zijlstra (Intel)
---
Change in v2
On 4/27/2025 2:21 AM, Mi, Dapeng wrote:
Reviewed-by: Dapeng Mi
Thanks!
I just sent out v4, so unless a v5 is needed, leave it to our x86
maintainers.
hile at it, convert the data type of MSR index to u32 in functions
called in pmu_msr_chk_emulated().
Suggested-by: H. Peter Anvin (Intel)
Suggested-by: Juergen Gross
Signed-off-by: Xin Li (Intel)
Reviewed-by: Juergen Gross
Acked-by: Peter Zijlstra (Intel)
---
Change in v4:
*) Remove two &quo
rdpmc() is not used anywhere, remove it.
Signed-off-by: Xin Li (Intel)
Acked-by: Dave Hansen
Acked-by: Peter Zijlstra (Intel)
---
arch/x86/include/asm/msr.h | 7 ---
arch/x86/include/asm/paravirt.h | 7 ---
2 files changed, 14 deletions(-)
diff --git a/arch/x86/include/asm/msr.h
Now that rdpmc() is gone, i.e. rdpmcl() is the sole PMC read helper,
simply rename rdpmcl() to rdpmc().
Signed-off-by: Xin Li (Intel)
Acked-by: Dave Hansen
Acked-by: Peter Zijlstra (Intel)
---
Changes in v3:
*) Explain the reason of the renaming in the changelog (Dave Hansen).
*) Use shorter
ve the way for improving MSR API names, convert __rdmsr()
uses to native_rdmsrq() to ensure consistent usage. Later, these
APIs can be renamed to better reflect their implications, such as
native or pvops, with or without trace, and safe or non-safe.
No functional change intended.
Signed-off-by:
1-...@zytor.com/
This patch series is based on:
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git x86/msr
Xin Li (Intel) (15):
x86/msr: Add missing includes of
x86/msr: Move rdtsc{,_ordered}() to
x86/msr: Remove rdpmc()
x86/msr: Rename rdpmcl() to rdpmc()
x86/msr: Convert the rdp
The pv_ops PMC read API is defined as:
u64 (*read_pmc)(int counter);
But Xen PMC read functions return unsigned long long, make them
return u64 consistently.
Signed-off-by: Xin Li (Intel)
Reviewed-by: Juergen Gross
Acked-by: Peter Zijlstra (Intel)
---
arch/x86/xen/pmu.c | 6
safe APIs.
Remove the error pointer argument.
Signed-off-by: Xin Li (Intel)
Reviewed-by: Juergen Gross
Acked-by: Peter Zijlstra (Intel)
---
Change in v3:
*) Fix a typo: set_reg() => set_seg() (Juergen Gross).
---
arch/x86/xen/enlighten_pv.c | 16 +---
1 file changed, 5 inserti
, refactor pv_cpu_ops.write_msr{_safe}() to accept an MSR value
in a single u64 argument, replacing the current dual u32 arguments.
No functional change intended.
Signed-off-by: Xin Li (Intel)
Reviewed-by: Juergen Gross
Acked-by: Peter Zijlstra (Intel)
---
Change in v2:
* Spell out the reason why use a
way.
While at it, convert leftover MSR data type "unsigned int" to u32.
Signed-off-by: Xin Li (Intel)
Acked-by: Peter Zijlstra (Intel)
---
arch/x86/include/asm/msr.h| 21 +++--
arch/x86/include/asm/paravirt.h | 19 ---
arch/x86/i
native_write_msr{,_safe}(), which
has now been removed.
[1]:
https://lore.kernel.org/lkml/0ec48b84-d158-47c6-b14c-3563fd14b...@zytor.com/
Suggested-by: H. Peter Anvin (Intel)
Sign-off-by: Xin Li (Intel)
Reviewed-by: Juergen Gross
Acked-by: Peter Zijlstra (Intel)
---
Change in v3:
*) Rename pmu_msr_{read
enamed to better reflect their implications,
such as native or pvops, with or without trace, and safe or
non-safe.
No functional change intended.
Signed-off-by: Xin Li (Intel)
Acked-by: Peter Zijlstra (Intel)
---
Change in v2:
* Use native_wrmsr() where natural [rmid_p, closid_p] high/lo para
The third argument in wrmsr(msr, low, 0) is unnecessary. Instead, use
wrmsrq(msr, low), which automatically sets the higher 32 bits of the
MSR value to 0.
Signed-off-by: Xin Li (Intel)
Acked-by: Peter Zijlstra (Intel)
---
arch/x86/hyperv/hv_apic.c | 6 +++---
arch/x86/include
the returned value, further enhancing
readability.
Signed-off-by: Xin Li (Intel)
Acked-by: Dave Hansen
Acked-by: Peter Zijlstra (Intel)
---
Change in v3:
*) Add a changelog even it's obvious (Dave Hansen).
---
arch/x86/events/amd/uncore.c | 2 +-
arch/x86/events/c
On 4/25/2025 3:08 AM, Jürgen Groß wrote:
Can you please remove the two "else" instances above? With directly
returning
form the "if" clause they are no longer needed.
I thought about it but forgot to do it later.
With that you can add my:
Reviewed-by: Juergen Gross
Thanks a lot!
On 4/25/2025 8:45 AM, Ilpo Järvinen wrote:
To me this looks really a random set of source files, maybe it helped some
build success but it's hard for me to review this because there are still
cases that depend on indirect include chains.
Could you just look into solving all missing msr.h include
hile at it, convert the data type of MSR index to u32 in functions
called in pmu_msr_chk_emulated().
Suggested-by: H. Peter Anvin (Intel)
Suggested-by: Juergen Gross
Signed-off-by: Xin Li (Intel)
---
Change in v3:
*) Remove the "emul" argument of pmu_msr_chk_emulated() (Juergen Gross
-off-by: Xin Li (Intel)
Acked-by: Dave Hansen
---
Change in v3:
* Add a problem statement to the changelog (Dave Hansen).
---
arch/x86/events/msr.c | 3 +
arch/x86/events/perf_event.h | 1 +
arch/x86/events/probe.c | 2 +
arch/x86
The third argument in wrmsr(msr, low, 0) is unnecessary. Instead, use
wrmsrq(msr, low), which automatically sets the higher 32 bits of the
MSR value to 0.
Signed-off-by: Xin Li (Intel)
---
arch/x86/hyperv/hv_apic.c | 6 +++---
arch/x86/include/asm/apic.h | 2
Now that rdpmc() is gone, i.e. rdpmcl() is the sole PMC read helper,
simply rename rdpmcl() to rdpmc().
Signed-off-by: Xin Li (Intel)
Acked-by: Dave Hansen
---
Changes in v3:
*) Explain the reason of the renaming in the changelog (Dave Hansen).
*) Use shorter name rdpmc() instead of rdpmcq
, refactor pv_cpu_ops.write_msr{_safe}() to accept an MSR value
in a single u64 argument, replacing the current dual u32 arguments.
No functional change intended.
Signed-off-by: Xin Li (Intel)
Reviewed-by: Juergen Gross
---
Change in v2:
* Spell out the reason why use a single u64 argument to pass the
safe APIs.
Remove the error pointer argument.
Signed-off-by: Xin Li (Intel)
Reviewed-by: Juergen Gross
---
Change in v3:
*) Fix a typo: set_reg() => set_seg() (Juergen Gross).
---
arch/x86/xen/enlighten_pv.c | 16 +---
1 file changed, 5 insertions(+), 11 deletions(-)
diff --gi
native_write_msr{,_safe}(), which
has now been removed.
[1]:
https://lore.kernel.org/lkml/0ec48b84-d158-47c6-b14c-3563fd14b...@zytor.com/
Suggested-by: H. Peter Anvin (Intel)
Sign-off-by: Xin Li (Intel)
---
Change in v3:
*) Rename pmu_msr_{read,write}() to pmu_msr_{read,write}_emulated()
(Dapeng Mi
rdpmc() is not used anywhere, remove it.
Signed-off-by: Xin Li (Intel)
Acked-by: Dave Hansen
---
arch/x86/include/asm/msr.h | 7 ---
arch/x86/include/asm/paravirt.h | 7 ---
2 files changed, 14 deletions(-)
diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h
enamed to better reflect their implications,
such as native or pvops, with or without trace, and safe or
non-safe.
No functional change intended.
Signed-off-by: Xin Li (Intel)
---
Change in v2:
* Use native_wrmsr() where natural [rmid_p, closid_p] high/lo parameters
can be used, without the
way.
While at it, convert leftover MSR data type "unsigned int" to u32.
Signed-off-by: Xin Li (Intel)
---
arch/x86/include/asm/msr.h| 21 +++--
arch/x86/include/asm/paravirt.h | 19 ---
arch/x86/include/asm/paravirt_types.h | 6 +++---
linux/kernel/git/tip/tip.git x86/msr
Xin Li (Intel) (14):
x86/msr: Move rdtsc{,_ordered}() to
x86/msr: Remove rdpmc()
x86/msr: Rename rdpmcl() to rdpmc()
x86/msr: Convert the rdpmc() macro into an always inline function
x86/msr: Return u64 consistently in Xen PMC read functions
x8
ve the way for improving MSR API names, convert __rdmsr()
uses to native_rdmsrq() to ensure consistent usage. Later, these
APIs can be renamed to better reflect their implications, such as
native or pvops, with or without trace, and safe or non-safe.
No functional change intended.
Signed-off-by:
The pv_ops PMC read API is defined as:
u64 (*read_pmc)(int counter);
But Xen PMC read functions return unsigned long long, make them
return u64 consistently.
Signed-off-by: Xin Li (Intel)
Reviewed-by: Juergen Gross
---
arch/x86/xen/pmu.c | 6 +++---
arch/x86/xen/xen-ops.h | 2
the returned value, further enhancing
readability.
Signed-off-by: Xin Li (Intel)
Acked-by: Dave Hansen
---
Change in v3:
*) Add a changelog even it's obvious (Dave Hansen).
---
arch/x86/events/amd/uncore.c | 2 +-
arch/x86/events/core.c| 2 +-
arch/x86/e
() is directly used when it needs to return an MSR
value in a u64 integer.
Add the native_rdmsrq() helper, which is simply an alias of __rdmsr(),
to make native_rdmsr() and native_rdmsrq() a pair of MSR read APIs.
Signed-off-by: Xin Li (Intel)
---
Change in v2:
* Split into two changes and add the
By the way, this patch should have "xen" in its subject tag.
Right, I should add it.
On 4/24/2025 3:11 AM, Jürgen Groß wrote:
set_seg(), please (further up, too).
Good catch, thanks a lot!
On 4/24/2025 3:05 AM, Jürgen Groß wrote:
May I suggest to get rid of the "emul" parameter of pmu_msr_chk_emulated()?
It has no real value, as pmu_msr_chk_emulated() could easily return
false in
the cases where it would set *emul to false.
Good idea!
The function type is a bit of weird but I
On 4/23/2025 9:05 AM, Jürgen Groß wrote:
It's not a major change, but when it is patched to use the immediate
form MSR write instruction, it's straightforwardly streamlined.
It should be rather easy to switch the current wrmsr/rdmsr paravirt
patching
locations to use the rdmsr/wrmsr instructi
On 4/24/2025 12:43 AM, Mi, Dapeng wrote:
These 2 patches are not complicated, it won't be difficult to review if
merging them into one as long as the commit message mentions it clearly.
Anyway I'm fine if you hope to keep them into two patches.
Simple Small Steps...
On 4/23/2025 11:33 PM, Mi, Dapeng wrote:
Could we merge this patch and previous patch into a single patch? It's
unnecessary to just modify the pmu_msr_read()/pmu_msr_write() in previous
patch and delete them immediately. It just wastes the effort.
No, it's not wasting effort, it's for easier re
On 4/23/2025 11:25 PM, Mi, Dapeng wrote:
-bool pmu_msr_read(unsigned int msr, uint64_t *val, int *err)
+bool pmu_msr_read(u32 msr, u64 *val)
The function name is some kind of misleading right now. With the change,
this function only read PMU MSR's value if it's emulated, otherwise it
won't rea
On 4/23/2025 8:51 AM, Dave Hansen wrote:
On 4/22/25 01:21, Xin Li (Intel) wrote:
static __always_inline void sev_es_wr_ghcb_msr(u64 val)
{
- u32 low, high;
-
- low = (u32)(val);
- high = (u32)(val >> 32);
-
- native_wrmsr(MSR_AMD64_SEV_ES_GHCB, low
On 4/23/2025 8:06 AM, Dave Hansen wrote:
On 4/23/25 07:28, Sean Christopherson wrote:
Now that rdpmc() is gone, i.e. rdpmcl/rdpmcq() is the only helper, why not
simply
rename rdpmcl() => rdpmc()? I see no point in adding a 'q' qualifier; it
doesn't
disambiguate anything and IMO is pure noise.
On 4/23/2025 7:13 AM, Dave Hansen wrote:
On 4/22/25 01:21, Xin Li (Intel) wrote:
Relocate rdtsc{,_ordered}() from to , and
subsequently remove the inclusion of in .
Consequently, must be included in several source files
that previously did not require it.
I know it's mildly obviou
On 4/23/2025 8:51 AM, Dave Hansen wrote:
On 4/22/25 01:21, Xin Li (Intel) wrote:
static __always_inline void sev_es_wr_ghcb_msr(u64 val)
{
- u32 low, high;
-
- low = (u32)(val);
- high = (u32)(val >> 32);
-
- native_wrmsr(MSR_AMD64_SEV_ES_GHCB, low
On 4/22/2025 4:12 AM, Jürgen Groß wrote:
+
+static __always_inline bool __rdmsrq(u32 msr, u64 *val, int type)
+{
+ bool ret;
+
+#ifdef CONFIG_XEN_PV
+ if (cpu_feature_enabled(X86_FEATURE_XENPV))
+ return __xenpv_rdmsrq(msr, val, type);
I don't think this will work for the Xen PV ca
On 4/22/2025 8:09 AM, Sean Christopherson wrote:
On Tue, Apr 22, 2025, Xin Li (Intel) wrote:
__rdmsr() is the lowest level primitive MSR read API, and its direct
use is NOT preferred.
Doesn't mean it's wrong.
I wouldn't go so far as to claim that it's wrong :-)
Use
On 4/22/2025 2:57 AM, Jürgen Groß wrote:
On 22.04.25 10:22, Xin Li (Intel) wrote:
The story started from tglx's reply in [1]:
For actual performance relevant code the current PV ops mechanics
are a horrorshow when the op defaults to the native instruction.
look at w
On 4/22/2025 2:28 AM, Juergen Gross wrote:
I have worked rather hard to make it less intrusive, especially by removing
the paravirt specific code patching (now all done via alternative patching)
and by removing 32-bit Xen PV mode.
I looked at the optimization, and it is a nice improvement.
On 4/22/2025 8:03 AM, Sean Christopherson wrote:
On Tue, Apr 22, 2025, Xin Li (Intel) wrote:
base-commit: f30a0c0d2b08b355c01392538de8fc872387cb2b
This commit doesn't exist in Linus' tree or the tip tree, and the series doesn't
apply cleanly on any of the "obvious"
On 4/22/2025 1:59 AM, Jürgen Groß wrote:
On 22.04.25 10:22, Xin Li (Intel) wrote:
To eliminate the indirect call overhead introduced by the pv_ops API,
utilize the alternatives mechanism to read MSR:
1) When built with !CONFIG_XEN_PV, X86_FEATURE_XENPV becomes a
disabled feature
On 4/22/2025 1:38 AM, Jürgen Groß wrote:
On 22.04.25 10:21, Xin Li (Intel) wrote:
To eliminate the indirect call overhead introduced by the pv_ops API,
use the alternatives mechanism to read PMC:
Which indirect call overhead? The indirect call is patched via the
alternative mechanism to a
rdpmc() is not used anywhere, remove it.
Signed-off-by: Xin Li (Intel)
---
arch/x86/include/asm/msr.h | 7 ---
arch/x86/include/asm/paravirt.h | 7 ---
2 files changed, 14 deletions(-)
diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h
index 2caa13830e11
native_rdmsrq() doesn't do trace thus can be used in noinstr context,
rename it to native_rdmsrq_no_trace() to make it explicit.
Signed-off-by: Xin Li (Intel)
---
arch/x86/boot/startup/sme.c | 4 ++--
arch/x86/events/amd/brs.c | 2 +-
arch/x86/hyperv/hv_
alternatives pattern, possibly invoking a
different exception handling pattern there, or at least indicating the
"real" location of the fault.
Signed-off-by: H. Peter Anvin (Intel)
Signed-off-by: Xin Li (Intel)
---
arch/x86/include/asm/asm.h | 6 +
arch/x86/include/a
Signed-off-by: Xin Li (Intel)
---
arch/x86/include/asm/msr.h | 4 ++--
arch/x86/kvm/svm/svm.c | 6 +++---
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h
index 72a1c3301d46..a1c63bed14be 100644
--- a/arch/x86/include/asm
native_rdmsr() doesn't do trace thus can be used in noinstr context,
rename it to native_rdmsr_no_trace() to make it explicit.
Signed-off-by: Xin Li (Intel)
---
arch/x86/include/asm/microcode.h | 2 +-
arch/x86/include/asm/msr.h| 8
arch/x86/kernel/cpu/microcode/
n handling
pattern there, or at least indicating the "real" location of the fault.
patches 21 and 22 refactor the code to use the alternatives mechanism to
read and write MSR.
Patches 23 ~ 34 are afterwards cleanups.
H. Peter Anvin (Intel) (1):
x86/extable: Implement EX_TYPE_FUNC_REWIND
Use native MSR API __native_{wr,rd}msrq() instead of MSR assemely.
Signed-off-by: Xin Li (Intel)
---
arch/x86/kernel/cpu/mce/core.c | 55 +-
1 file changed, 35 insertions(+), 20 deletions(-)
diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce
Convert native_rdmsr_no_trace() uses to native_rdmsrq_no_trace() uses
cleanly with the use of struct msr, and remove native_rdmsr_no_trace().
Signed-off-by: Xin Li (Intel)
---
arch/x86/include/asm/microcode.h | 6 +++---
arch/x86/include/asm/msr.h| 13 +++--
arch/x86
native_wrmsrq() doesn't do trace thus can be used in noinstr context,
rename it to native_wrmsrq_no_trace() to make it explicit.
Signed-off-by: Xin Li (Intel)
---
arch/x86/events/amd/brs.c | 2 +-
arch/x86/hyperv/ivm.c | 2 +-
arch/x86/include/asm/a
ism is also used to choose the new immediate
form MSR write instruction when it's available.
Consequently, remove the pv_ops MSR write APIs and the Xen callbacks.
[1]: https://lore.kernel.org/lkml/87y1h81ht4.ffs@tglx/
Originally-by: H. Peter Anvin (Intel)
Signed-off-by: Xin Li (Intel)
-
native_wrmsr() doesn't do trace thus can be used in noinstr context,
rename it to native_wrmsr_no_trace() to make it explicit.
Signed-off-by: Xin Li (Intel)
---
arch/x86/include/asm/msr.h| 8
arch/x86/kernel/cpu/resctrl/pseudo_lock.c | 4 ++--
2 files chang
Signed-off-by: Xin Li (Intel)
---
arch/x86/hyperv/ivm.c | 2 +-
arch/x86/include/asm/msr.h | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/x86/hyperv/ivm.c b/arch/x86/hyperv/ivm.c
index dfddf522e838..8860c6c0f013 100644
--- a/arch/x86/hyperv/ivm.c
+++ b/arch
Signed-off-by: Xin Li (Intel)
---
arch/x86/include/asm/msr.h | 4 ++--
arch/x86/kernel/kvmclock.c | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h
index 2a62a899f7a5..72a1c3301d46 100644
--- a/arch/x86/include/asm
Signed-off-by: Xin Li (Intel)
---
arch/x86/include/asm/msr.h | 4 ++--
arch/x86/kvm/svm/svm.c | 10 +-
arch/x86/xen/pmu.c | 4 ++--
3 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h
index 4c7aa9e7fbac
Since the ARGS macros are no longer used in the MSR read/write API
implementation, move them after their definitions.
Signed-off-by: Xin Li (Intel)
---
arch/x86/include/asm/msr.h | 38 +-
1 file changed, 21 insertions(+), 17 deletions(-)
diff --git a/arch
ed to change, but the approaches
how they perform MSR operations are binary patched during boot time upon
availability of MSR instructions.
Signed-off-by: Xin Li (Intel)
---
arch/x86/boot/startup/sme.c | 4 ++--
arch/x86/events/amd/brs.c | 2 +-
arch/x86/hyperv/hv_
Signed-off-by: Xin Li (Intel)
---
arch/x86/hyperv/hv_apic.c | 6 +++---
arch/x86/include/asm/apic.h | 2 +-
arch/x86/include/asm/switch_to.h | 2 +-
arch/x86/kernel/cpu/amd.c | 2 +-
arch/x86/kernel/cpu/common.c | 8
feature bit for MSR immediate form instructions.
Suggested-by: Borislav Petkov (AMD)
Signed-off-by: Xin Li (Intel)
---
arch/x86/include/asm/cpufeatures.h | 1 +
arch/x86/kernel/cpu/scattered.c| 1 +
2 files changed, 2 insertions(+)
diff --git a/arch/x86/include/asm/cpufeatures.h
b/arch/x86
Signed-off-by: Xin Li (Intel)
---
arch/x86/events/amd/uncore.c | 2 +-
arch/x86/events/core.c| 2 +-
arch/x86/events/intel/core.c | 4 ++--
arch/x86/events/intel/ds.c| 2 +-
arch/x86/include/asm/msr.h| 2 +-
arch
As pmu_msr_{read,write}() are now wrappers of pmu_msr_chk_emulated(),
remove them and use pmu_msr_chk_emulated() directly.
While at it, convert the data type of MSR index to u32 in functions
called in pmu_msr_chk_emulated().
Suggested-by: H. Peter Anvin (Intel)
Signed-off-by: Xin Li (Intel
Relocate rdtsc{,_ordered}() from to , and
subsequently remove the inclusion of in .
Consequently, must be included in several source files
that previously did not require it.
Signed-off-by: Xin Li (Intel)
---
arch/x86/boot/startup/sme.c | 1 +
arch/x86/events/msr.c
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