Hi Julien,
On Tue, Nov 27, 2018 at 7:36 PM Julien Grall wrote:
>
>
>
> On 11/17/18 4:01 PM, Mirela Simonovic wrote:
> > Hi,
>
> Hi Mirela,
>
> >
> > On Sat, Nov 17, 2018 at 12:06 AM Stefano Stabellini
> > wrote:
> >>
> >> On Sat, 17
Hi,
On Sat, Nov 17, 2018 at 5:02 PM Mirela Simonovic
wrote:
>
> On Sat, Nov 17, 2018 at 5:01 PM Mirela Simonovic
> wrote:
> >
> > Hi,
> >
> > On Sat, Nov 17, 2018 at 12:06 AM Stefano Stabellini
> > wrote:
> > >
> > > On Sat, 17 Nov 201
On Sat, Nov 17, 2018 at 5:01 PM Mirela Simonovic
wrote:
>
> Hi,
>
> On Sat, Nov 17, 2018 at 12:06 AM Stefano Stabellini
> wrote:
> >
> > On Sat, 17 Nov 2018, Dario Faggioli wrote:
> > > On Fri, 2018-11-16 at 21:58 +, Julien Grall wrote:
> > >
Hi,
On Sat, Nov 17, 2018 at 12:06 AM Stefano Stabellini
wrote:
>
> On Sat, 17 Nov 2018, Dario Faggioli wrote:
> > On Fri, 2018-11-16 at 21:58 +, Julien Grall wrote:
> > > On 16/11/2018 21:41, Mirela Simonovic wrote:
> > > > On Fri, Nov 16, 2018 at 8:09 PM
Hi Stefano,
On Fri, Nov 16, 2018 at 8:09 PM Stefano Stabellini
wrote:
>
> On Fri, 16 Nov 2018, Stefano Stabellini wrote:
> > On Fri, 16 Nov 2018, Julien Grall wrote:
> > > On 16/11/2018 12:34, Mirela Simonovic wrote:
> > > > Hi Julien,
> > >
> > &
Hi Julien,
On Fri, Nov 16, 2018 at 12:44 PM Julien Grall wrote:
>
>
>
> On 16/11/2018 11:29, Mirela Simonovic wrote:
> > On Fri, Nov 16, 2018 at 11:33 AM Mirela Simonovic
> > wrote:
> >>
> >> Hi Julien,
> >>
> >> On Thu,
On Fri, Nov 16, 2018 at 11:33 AM Mirela Simonovic
wrote:
>
> Hi Julien,
>
> On Thu, Nov 15, 2018 at 9:31 PM Julien Grall wrote:
> >
> > Hi,
> >
> > On 11/12/18 11:30 AM, Mirela Simonovic wrote:
> > > The resume of Dom0 should always follow Xen's
Hi Julien,
On Thu, Nov 15, 2018 at 9:31 PM Julien Grall wrote:
>
> Hi,
>
> On 11/12/18 11:30 AM, Mirela Simonovic wrote:
> > The resume of Dom0 should always follow Xen's resume. This is
> > done by unblocking the first vCPU of Dom0.
>
> Please explain
Hi Julien,
On Thu, Nov 15, 2018 at 7:23 PM Julien Grall wrote:
>
> Hi Mirela,
>
> On 11/12/18 11:30 AM, Mirela Simonovic wrote:
> > When Dom0 finalizes its suspend procedure the suspend of Xen is
> > triggered by calling system_suspend(). Dom0 finalizes the suspend from
&
Hi Julien,
On Wed, Nov 14, 2018 at 7:48 PM Julien Grall wrote:
>
> Hi,
>
> On 14/11/2018 17:35, Mirela Simonovic wrote:
> > On Wed, Nov 14, 2018 at 6:10 PM Julien Grall wrote:
> >> On 14/11/2018 15:40, Mirela Simonovic wrote:
> >>> On Wed, Nov 14, 2018 at
Hi Julien,
On Thu, Nov 15, 2018 at 12:38 PM Julien Grall wrote:
>
> Hi,
>
> On 11/15/18 11:10 AM, Mirela Simonovic wrote:
> > Hi Julien,
> >
> > On Thu, Nov 15, 2018 at 11:59 AM Julien Grall wrote:
> >>
> >> Hi Mirela,
> >>
> >>
Hi Julien,
On Thu, Nov 15, 2018 at 11:59 AM Julien Grall wrote:
>
> Hi Mirela,
>
> On 11/15/18 10:33 AM, Mirela Simonovic wrote:
> > On Thu, Nov 15, 2018 at 11:26 AM Andrew Cooper
> > wrote:
> >>
> >> On 15/11/2018 10:13, Julien Grall wrote:
> &
On Thu, Nov 15, 2018 at 11:26 AM Andrew Cooper
wrote:
>
> On 15/11/2018 10:13, Julien Grall wrote:
> > (+ Andre)
> >
> > On 11/15/18 12:47 AM, Andrew Cooper wrote:
> >> On 14/11/2018 12:49, Julien Grall wrote:
> >>> Hi Mirela,
> >&
Hi Julien,
On Wed, Nov 14, 2018 at 6:10 PM Julien Grall wrote:
>
> Hi Mirela,
>
> On 14/11/2018 15:40, Mirela Simonovic wrote:
> > On Wed, Nov 14, 2018 at 4:07 PM Julien Grall wrote:
> >> On 12/11/2018 11:30, Mirela Simonovic wrote:
> >>> When Dom0 finaliz
Hi Julien,
On Wed, Nov 14, 2018 at 4:07 PM Julien Grall wrote:
>
> Hi,
>
> On 12/11/2018 11:30, Mirela Simonovic wrote:
> > When Dom0 finalizes its suspend procedure the suspend of Xen is
> > triggered by calling system_suspend(). Dom0 finalizes the suspend from
> >
On Wed, Nov 14, 2018 at 4:36 PM Mirela Simonovic
wrote:
>
> Hi Julien,
>
> On Wed, Nov 14, 2018 at 3:49 PM Julien Grall wrote:
> >
> >
> >
> > On 14/11/2018 13:05, Julien Grall wrote:
> > >
> > >
> > > On 14/11/2018
Hi Julien,
On Wed, Nov 14, 2018 at 3:49 PM Julien Grall wrote:
>
>
>
> On 14/11/2018 13:05, Julien Grall wrote:
> >
> >
> > On 14/11/2018 12:35, Mirela Simonovic wrote:
> >> Hi Julien,
> >
> > Hi,
> >
> >>
> >> On 11/14/2
On 11/14/2018 11:52 AM, Julien Grall wrote:
Hi Mirela,
On 12/11/2018 11:30, Mirela Simonovic wrote:
Non-boot CPUs have to be disabled on suspend and enabled on resume
(hotplug-based mechanism). Disabling non-boot CPUs will lead to PSCI
CPU_OFF to be called by each non-boot CPU. Depending on
?
disable_nonboot_cpus will lead to CPU_OFF PSCI to be called. That is
orthogonal to suspend support in this series
On 12/11/2018 11:30, Mirela Simonovic wrote:
System suspend may lead to a state where GIC would be powered down.
Therefore, Xen should save/restore the context of GIC on suspend
On 11/13/2018 04:09 PM, Julien Grall wrote:
On 13/11/2018 10:23, Julien Grall wrote:
Hi,
On 12/11/2018 11:30, Mirela Simonovic wrote:
+/*
+ * This function sets the context of current VCPU to the state
which is expected
+ * by the guest on resume. The expected VCPU state is:
+ * 1) pc
Hi Julien,
On 11/14/2018 11:45 AM, Julien Grall wrote:
Hi,
On 13/11/2018 20:39, Stefano Stabellini wrote:
On Mon, 12 Nov 2018, Julien Grall wrote:
However, what is the issue with saving all the registers here?
We need to save arguments that are provided by a guest with system
suspend PSCI
On 11/13/2018 09:32 AM, Andrew Cooper wrote:
On 12/11/2018 19:56, Julien Grall wrote:
Hi Andrew,
On 11/12/18 4:41 PM, Andrew Cooper wrote:
On 12/11/18 16:35, Mirela Simonovic wrote:
diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c
index e594b48d81..7f8105465c 100644
--- a/xen
On Wed, Nov 14, 2018 at 1:14 AM Stefano Stabellini
wrote:
>
> On Mon, 12 Nov 2018, Mirela Simonovic wrote:
> > PSCI system suspend function shall be invoked to finalize Xen suspend
> > procedure. Resume entry point, which needs to be passed via 1st argument
> > of PSCI sy
On Wed, Nov 14, 2018 at 10:13 AM Julien Grall wrote:
>
> Hi Stefano,
>
> On 11/13/18 11:41 PM, Stefano Stabellini wrote:
> > On Mon, 12 Nov 2018, Mirela Simonovic wrote:
> >> System suspend may lead to a state where GIC would be powered down.
> >> Therefore, Xe
On Mon, Nov 12, 2018 at 2:15 PM Julien Grall wrote:
>
> Hi Mirela,
>
> On 11/12/18 11:30 AM, Mirela Simonovic wrote:
> > From: Saeed Nowshadi
> >
> > The arch_set_info_guest() has code to initialize the context of a VCPU.
> > When a VCPU is resumed it
Hi,
On Tue, Nov 13, 2018 at 10:43 AM Julien Grall wrote:
>
> Hi Stefano,
>
> On 12/11/2018 23:46, Stefano Stabellini wrote:
> > On Mon, 12 Nov 2018, Julien Grall wrote:
> >> Hi,
> >>
> >> On 11/12/18 11:30 AM, Mirela Simonovic wrote:
> >>>
Hi Julien,
On Mon, Nov 12, 2018 at 6:00 PM Julien Grall wrote:
>
>
>
> On 11/12/18 4:52 PM, Mirela Simonovic wrote:
> > Hi Julien,
>
> Hi,
>
> > Thanks for the feedback.
> >
> > On Mon, Nov 12, 2018 at 4:36 PM Julien Grall wrote:
> >>
Hi Julien,
Thanks for the feedback.
On Mon, Nov 12, 2018 at 4:36 PM Julien Grall wrote:
>
> Hi Mirela,
>
> On 11/12/18 11:30 AM, Mirela Simonovic wrote:
> > GIC and virtual timer context must be saved when the domain suspends.
>
> Please provide the rationale for thi
Hi Julien,
Thanks for your feedback, I'll need to answer in iterations.
On Mon, Nov 12, 2018 at 4:27 PM Julien Grall wrote:
>
> Hi Mirela,
>
> On 11/12/18 11:30 AM, Mirela Simonovic wrote:
> > The implementation consists of:
> > -Adding PSCI system susp
Hi Jan,
On Mon, Nov 12, 2018 at 4:23 PM Jan Beulich wrote:
>
> >>> On 12.11.18 at 16:17, wrote:
> > Hi Jan,
> >
> > On Mon, Nov 12, 2018 at 12:47 PM Jan Beulich wrote:
> >>
> >> >>> On 12.11.18 at 12:30, wrote:
> >> > --- a/xen/include/xen/timer.h
> >> > +++ b/xen/include/xen/timer.h
> >> > @@
Hi Jan,
On Mon, Nov 12, 2018 at 12:47 PM Jan Beulich wrote:
>
> >>> On 12.11.18 at 12:30, wrote:
> > --- a/xen/include/xen/timer.h
> > +++ b/xen/include/xen/timer.h
> > @@ -18,6 +18,9 @@ struct timer {
> > /* System time expiry value (nanoseconds since boot). */
> > s_time_t expires;
>
Hi Julien,
On Mon, Nov 12, 2018 at 1:08 PM Julien Grall wrote:
>
> On 11/12/18 12:01 PM, Mirela Simonovic wrote:
> > Hi Julien,
>
> Hi Mirela,
>
> Please configure your e-mail client to avoid quoting using "space".
> Otherwise, this is going to make difficu
Hi Julien,
On Mon, Nov 12, 2018 at 12:50 PM Julien Grall wrote:
> Hi Mirela,
>
> Thank you for posting the series. Could you provide a branch with the
> patch applied?
>
>
I have applied patches on top of upstream/staging.
> On 11/12/18 11:30 AM, M
What?
On Mon, Nov 12, 2018 at 12:42 PM Jan Beulich wrote:
> >>> On 12.11.18 at 12:30, wrote:
> > --- a/xen/include/xen/sched.h
> > +++ b/xen/include/xen/sched.h
> > @@ -24,6 +24,7 @@
> > #include
> > #include
> > #include
> > +#include
> > #include
> > #include
> > #include
>
> Why
Hi,
One thing I screwed - I forgot to remove changes log from an internal
review, so please ignore it. This is officially the first version.
Thanks,
Mirela
On Mon, Nov 12, 2018 at 12:31 PM Mirela Simonovic <
mirela.simono...@aggios.com> wrote:
> This series contains support for suspe
/restored on context switch.
Tested on Xilinx Ultrascale+ MPSoC with (and without) powering down
the GIC.
Signed-off-by: Mirela Simonovic
Signed-off-by: Saeed Nowshadi
---
xen/arch/arm/gic-v2.c | 147 ++
xen/arch/arm/gic.c| 27 +
xen
This is done using generic console_suspend/resume functions that cause
uart driver specific suspend/resume handlers to be called for each
initialized port (if the port has suspend/resume driver handlers
implemented).
Signed-off-by: Mirela Simonovic
Signed-off-by: Saeed Nowshadi
---
xen/arch
2nd argument of system suspend PSCI call, is unused, as in Linux.
Signed-off-by: Mirela Simonovic
Signed-off-by: Saeed Nowshadi
---
Changes in v2:
-The commit message was stale - referring to the do_suspend function
that has been renamed long time ago. Fixed commit message
---
xen/arch/arm
timer code to reprogram the EL2 timer
as needed. Enabling of EL1 physical timer will be triggered by an
entity which uses it.
Signed-off-by: Mirela Simonovic
Signed-off-by: Saeed Nowshadi
---
xen/arch/arm/suspend.c | 4
xen/arch/arm/time.c| 22 ++
xen
: Mirela Simonovic
---
xen/arch/arm/arm64/head.S | 265 --
1 file changed, 138 insertions(+), 127 deletions(-)
diff --git a/xen/arch/arm/arm64/head.S b/xen/arch/arm/arm64/head.S
index ef87b5c254..f95390dcfe 100644
--- a/xen/arch/arm/arm64/head.S
+++ b/xen
that the order of saving register context into cpu_context
structure has to match the order of restoring.
Since the suspend/resume is supported only for arm64, we define
a null cpu_context structure so arm32 could compile.
Signed-off-by: Mirela Simonovic
Signed-off-by: Saeed Nowshadi
---
xen/arch/
compatibility.
Signed-off-by: Mirela Simonovic
Signed-off-by: Saeed Nowshadi
---
xen/arch/arm/suspend.c | 34 ++
1 file changed, 34 insertions(+)
diff --git a/xen/arch/arm/suspend.c b/xen/arch/arm/suspend.c
index f2338e41db..21b45f8248 100644
--- a/xen/arch/arm/suspend.c
, we'll just
restore interrupts configuration and abort suspend.
Signed-off-by: Mirela Simonovic
Signed-off-by: Saeed Nowshadi
---
xen/arch/arm/suspend.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/xen/arch/arm/suspend.c b/xen/arch/arm/suspend.c
index 8e8e531d61..b7940
that a mapping cannot be both
writable and executable (this was configured prior to suspend).
This is done using an existing function (mmu_init_secondary_cpu).
Signed-off-by: Mirela Simonovic
Signed-off-by: Saeed Nowshadi
---
Changes in v2:
- Patch from v1:
"[XEN PATCH 17/21] xen/arm
The resume of Dom0 should always follow Xen's resume. This is
done by unblocking the first vCPU of Dom0.
Signed-off-by: Mirela Simonovic
Signed-off-by: Saeed Nowshadi
---
xen/arch/arm/suspend.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/xen/arch/arm/suspend.c b/xen/arc
Xilinx Zynq Ultrascale+ MPSoC (including power down of
each non-boot CPU).
Signed-off-by: Mirela Simonovic
Signed-off-by: Saeed Nowshadi
---
xen/arch/arm/suspend.c | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/xen/arch/arm/suspend.c b/xen/arch/arm/suspend.c
index
be
shared with the resume path.
Signed-off-by: Saeed Nowshadi
Signed-off-by: Mirela Simonovic
---
xen/arch/arm/domain.c| 34 +-
xen/include/xen/domain.h | 1 +
2 files changed, 22 insertions(+), 13 deletions(-)
diff --git a/xen/arch/arm/domain.c b/xen/arch
Freeze and thaw of domains is reused as implemented for x86. In
addition, system_state variable is updated to represent the actual
state of the system.
Signed-off-by: Mirela Simonovic
Signed-off-by: Saeed Nowshadi
---
xen/arch/arm/suspend.c | 8
1 file changed, 8 insertions(+)
diff
-by: Mirela Simonovic
Signed-off-by: Saeed Nowshadi
---
xen/arch/arm/suspend.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/xen/arch/arm/suspend.c b/xen/arch/arm/suspend.c
index dae1b1f7d6..8e8e531d61 100644
--- a/xen/arch/arm/suspend.c
+++ b/xen/arch/arm/suspend.c
@@ -133,6 +133,7 @@ static
---
The series does not include:
a) UART driver-specific suspend/resume that gets called when console suspends
b) SMMU suspend/resume
c) Suspend coordination support that would allow dom0 to request domUs to
suspend
These will be submitted in the following series.
Mirela Simonovic (16):
xen/a
is already reset, and
contains the right resume entry point in program counter that will be
restored in ctxt_switch_to(). The only thing that needs to be done at this
point is to clear the variables that marked the domain state as suspended.
Signed-off-by: Mirela Simonovic
Signed-off-by: Saeed Nowsha
structure.
Programming of the timers is triggered when a VCPU of the suspended
domain is scheduled in on resume.
Signed-off-by: Mirela Simonovic
Signed-off-by: Saeed Nowshadi
---
Changes in v2:
-Fixed typo in commit message
---
xen/arch/arm/domain.c | 1 +
xen/arch/arm/suspend.c | 3 +++
GIC and virtual timer context must be saved when the domain suspends.
This is done by moving the respective code in ctxt_switch_from()
before the return that happens if the domain suspended.
Signed-off-by: Mirela Simonovic
Signed-off-by: Saeed Nowshadi
---
xen/arch/arm/domain.c | 14
These functions will be reused by suspend/resume support for ARM.
Signed-off-by: Mirela Simonovic
Signed-off-by: Saeed Nowshadi
---
xen/arch/x86/acpi/power.c | 28
xen/common/domain.c | 29 +
xen/include/xen/sched.h | 3 +++
3
Hi Julien,
On Tue, Jun 5, 2018 at 8:00 PM, Julien Grall wrote:
>
>
> On 05/06/18 18:24, Julien Grall wrote:
>
>> Hi Mirela,
>>
>> On 01/06/18 14:17, Mirela Simonovic wrote:
>>
>>> Linux/dom0 accesses OSLSR register when saving CPU context during t
Hi,
On Wed, Jun 6, 2018 at 8:00 PM, Julien Grall wrote:
> (+ Stefano, Mirela, Juergen and Boris)
>
> On 06/06/18 09:17, moin anjnawala wrote:
>>
>> Hi Julien,
>
>
> Hi,
>
>> As you specified earlier I am now able to boot using xen4.10. I am
>> using linux4.4 as dom0 as well as domU.In domU, I hav
fine). However, when non-boot pCPUs are
hotplugged on resume, these interrupts are not migrated back to non-boot
pCPUs, i.e. IRQ affinity is not restored on resume (this is wrong).
This patch adds the restoration of IRQ affinity when a pCPU is hotplugged.
Signed-off-by: Mirela Simonovic
Reviewed-by:
be added with the suspend to RAM support for ARM, where the hotplug
of non-boot CPUs will be triggered via enable_nonboot_cpus() call.
Signed-off-by: Mirela Simonovic
---
CC: Stefano Stabellini
CC: Julien Grall
---
Changes in v2:
-Fix commit message
-Save configured VTCR_EL2 value into static
fixed value.
Signed-off-by: Mirela Simonovic
Reviewed-by: Stefano Stabellini
Acked-by: Julien Grall
---
CC: Stefano Stabellini
CC: Julien Grall
---
Changes in v2:
- Commit message fix (arm64 related change instead of arm)
- Add Stefano's reviewed-by
Changes in v3:
- Added Julien'
lling CPU couldn't be enabled afterwards (stays in WFI loop forever).
Note that if the PSCI version is higher than v0.1 the CPU_OFF will be
called regardless of the system state. This is done because scenarios
other than suspend may benefit from powering off the CPU.
Signed-off-by: Mirela Simono
Dario Faggioli
---
Mirela Simonovic (10):
xen/arm64: Added handling of the trapped access to OSLSR register
xen/arm: Ignore write to GICD_ISACTIVERn registers (vgic-v2)
xen/arm: Implement CPU_OFF PSCI call (physical interface)
xen/arm: Remove __initdata and __init to enable CPU hotplug
xe
.
Signed-off-by: Mirela Simonovic
Acked-by: Julien Grall
---
CC: Stefano Stabellini
CC: Julien Grall
---
Changes in v3:
-Use notifier to trigger remove_cpu_sibling_map() when the CPU dies.
Changes in v4:
-Initialize cpu_smpboot notifier at presmp_init rather than init phase
to cover the case where
few data structures and functions that are used within the cpu up flow.
Signed-off-by: Mirela Simonovic
Acked-by: Julien Grall
---
CC: Stefano Stabellini
CC: Julien Grall
---
Changes in v3:
- Added acked-by Julien
---
xen/arch/arm/arm64/smpboot.c | 2 +-
xen/arch/arm/irq.c | 2
his patch the interrupt will be
released when the CPU_DYING event is received by the callback which
is added in gic.c.
Signed-off-by: Mirela Simonovic
Acked-by: Julien Grall
---
CC: Stefano Stabellini
CC: Julien Grall
---
Changes in v3:
-Add notifier in order to trigger releasing of
->init_timer_interrupt->request_irq).
With this patch timers will be disabled and interrupts will be
released when the newly added callback receives CPU_DYING event.
Signed-off-by: Mirela Simonovic
Acked-by: Julien Grall
---
CC: Stefano Stabellini
CC: Julien Grall
---
Changes in v3:
-Trigger releas
always return success for CPU_STARTING
event, or the notify_cpu_starting() and other common code should be
fixed to expect an error at CPU_STARTING phase.
Signed-off-by: Mirela Simonovic
Reviewed-by: Julien Grall
---
CC: Stefano Stabellini
CC: Julien Grall
---
Changes in v4:
-Add includes
already handled as 'read as zero'.
Signed-off-by: Mirela Simonovic
Reviewed-by: Julien Grall
---
CC: Stefano Stabellini
CC: Julien Grall
---
Changes in v2:
- Write should be ignored only if the value to be written is zero
(in v1 the write was ignored regardless of the value)
Cha
On Wed, May 30, 2018 at 11:48 AM, Mirela Simonovic <
mirela.simono...@aggios.com> wrote:
> Hi Julien,
>
> Thanks for the feedback.
>
> On Tue, May 29, 2018 at 3:19 PM, Julien Grall
> wrote:
>
>> Hi,
>>
>>
>> On 15/05/18 12:44, Mirela Simonov
Hi Julien,
Thanks for the feedback.
On Tue, May 29, 2018 at 3:19 PM, Julien Grall wrote:
> Hi,
>
>
> On 15/05/18 12:44, Mirela Simonovic wrote:
>
>> Linux/dom0 accesses OSLSR register when saving CPU context during the
>> suspend procedure. Xen traps access t
Hi,
Could you please provide feedback for the remaining patches?
Thanks,
Mirela
On Tue, May 15, 2018 at 1:44 PM, Mirela Simonovic <
mirela.simono...@aggios.com> wrote:
> This patch set contains fixes that are required as precondition for
> suspend to
> RAM support, including
always return success for CPU_STARTING
event, or the notify_cpu_starting() and other common code should be
fixed to expect an error at CPU_STARTING phase.
Signed-off-by: Mirela Simonovic
---
CC: Stefano Stabellini
CC: Julien Grall
---
Changes in v4:
-Add includes alphabetically
-Added newline
be added with the suspend to RAM support for ARM, where the hotplug
of non-boot CPUs will be triggered via enable_nonboot_cpus() call.
Signed-off-by: Mirela Simonovic
---
CC: Stefano Stabellini
CC: Julien Grall
---
Changes in v2:
-Fix commit message
-Save configured VTCR_EL2 value into static
.
Signed-off-by: Mirela Simonovic
Reviewed-by: Stefano Stabellini
Acked-by: Julien Grall
---
CC: Stefano Stabellini
CC: Julien Grall
---
Changes in v2:
- Commit message fix (arm64 related change instead of arm)
- Add Stefano's reviewed-by
Changes in v3:
- Added Julien's acked-by
---
xe
few data structures and functions that are used within the cpu up flow.
Signed-off-by: Mirela Simonovic
Acked-by: Julien Grall
---
CC: Stefano Stabellini
CC: Julien Grall
---
Changes in v3:
- Added acked-by Julien
---
xen/arch/arm/arm64/smpboot.c | 2 +-
xen/arch/arm/irq.c | 2
Hi Stefano,
On Mon, May 14, 2018 at 6:59 PM, Stefano Stabellini
wrote:
> On Mon, 14 May 2018, Julien Grall wrote:
>> On 11/05/18 22:47, Stefano Stabellini wrote:
>> > On Fri, 11 May 2018, Dario Faggioli wrote:
>> > > On Fri, 2018-05-11 at 14:08 +0100, Julien Grall wrote:
>> > > > The whole idea h
->init_timer_interrupt->request_irq).
With this patch timers will be disabled and interrupts will be
released when the newly added callback receives CPU_DYING event.
Signed-off-by: Mirela Simonovic
---
CC: Stefano Stabellini
CC: Julien Grall
---
Changes in v3:
-Trigger releasing of timer interrupts
.
Signed-off-by: Mirela Simonovic
---
CC: Stefano Stabellini
CC: Julien Grall
---
Changes in v3:
-Use notifier to trigger remove_cpu_sibling_map() when the CPU dies.
Changes in v4:
-Initialize cpu_smpboot notifier at presmp_init rather than init phase
to cover the case where a secondary CPU dies
lling CPU couldn't be enabled afterwards (stays in WFI loop forever).
Note that if the PSCI version is higher than v0.1 the CPU_OFF will be
called regardless of the system state. This is done because scenarios
other than suspend may benefit from powering off the CPU.
Signed-off-by: Mirela Simono
n the last patch of the series errata notifier now returns an error
---
CC: Stefano Stabellini
CC: Julien Grall
CC: George Dunlap
CC: Dario Faggioli
---
Mirela Simonovic (10):
xen/arm64: Added handling of the trapped access to OSLSR register
xen/arm: Ignore write to GICD_ISACTIVERn registers
already handled as 'read as zero'.
Signed-off-by: Mirela Simonovic
Reviewed-by: Julien Grall
---
CC: Stefano Stabellini
CC: Julien Grall
---
Changes in v2:
- Write should be ignored only if the value to be written is zero
(in v1 the write was ignored regardless of the value)
Cha
fine). However, when non-boot pCPUs are
hotplugged on resume, these interrupts are not migrated back to non-boot
pCPUs, i.e. IRQ affinity is not restored on resume (this is wrong).
This patch adds the restoration of IRQ affinity when a pCPU is hotplugged.
Signed-off-by: Mirela Simonovic
Reviewed-by:
his patch the interrupt will be
released when the CPU_DYING event is received by the callback which
is added in gic.c.
Signed-off-by: Mirela Simonovic
Acked-by: Julien Grall
---
CC: Stefano Stabellini
CC: Julien Grall
---
Changes in v3:
-Add notifier in order to trigger releasing of
Hi,
On Fri, May 11, 2018 at 2:07 PM, Mirela Simonovic
wrote:
> Hi Julien,
>
> On Fri, May 11, 2018 at 12:54 PM, Julien Grall wrote:
>>
>>
>> On 11/05/18 11:41, Mirela Simonovic wrote:
>>>
>>> Hi Dario,
>>>
>>> On Thu, May 10, 2018 a
Hi Julien,
On Fri, May 11, 2018 at 12:54 PM, Julien Grall wrote:
>
>
> On 11/05/18 11:41, Mirela Simonovic wrote:
>>
>> Hi Dario,
>>
>> On Thu, May 10, 2018 at 6:24 PM, Dario Faggioli
>> wrote:
>>>
>>> On Thu, 2018-05-10 at 17:49 +0200,
Hi Dario,
On Thu, May 10, 2018 at 6:24 PM, Dario Faggioli wrote:
> On Thu, 2018-05-10 at 17:49 +0200, Mirela Simonovic wrote:
>> Regardless of the fact that the notifier returns an error or not, I
>> believe it would be good and safe to set priority and document that
>> prio
Hi Julien,
On Thu, May 10, 2018 at 5:13 PM, Julien Grall wrote:
>
>
> On 10/05/18 16:00, Mirela Simonovic wrote:
>>
>> Hi Dario,
>>
>> On Thu, May 10, 2018 at 4:25 PM, Dario Faggioli
>> wrote:
>>>
>>> On Thu, 2018-05-10 at 15:24 +0200, Mi
Hi Dario,
On Thu, May 10, 2018 at 4:25 PM, Dario Faggioli wrote:
> On Thu, 2018-05-10 at 15:24 +0200, Mirela Simonovic wrote:
>> On Thu, May 10, 2018 at 1:57 PM, Mirela Simonovic
>>
>> > Please take a look at function cpu_schedule_callback in schedule.c.
>> > Wit
Hi Julien,
On Thu, May 10, 2018 at 3:29 PM, Julien Grall wrote:
> Hi,
>
> On 05/10/2018 02:24 PM, Mirela Simonovic wrote:
>>
>> On Thu, May 10, 2018 at 1:57 PM, Mirela Simonovic
>> wrote:
>
>
>> I have tested the tuned scenario where enabling capabilities
On Thu, May 10, 2018 at 1:57 PM, Mirela Simonovic
wrote:
> Hi,
>
> +Dario
>
> On Wed, May 9, 2018 at 6:32 PM, Julien Grall wrote:
>>
>>
>> On 09/05/18 16:48, Mirela Simonovic wrote:
>>>
>>> Hi Julien,
>>
>>
>> Hi Mirel
Hi,
+Dario
On Wed, May 9, 2018 at 6:32 PM, Julien Grall wrote:
>
>
> On 09/05/18 16:48, Mirela Simonovic wrote:
>>
>> Hi Julien,
>
>
> Hi Mirela,
>
>
>> On Mon, Apr 30, 2018 at 6:09 PM, Julien Grall
>> wrote:
>>>
>>>
Hi Julien,
On Mon, Apr 30, 2018 at 6:09 PM, Julien Grall wrote:
> Hi Mirela,
>
>
> On 27/04/18 18:12, Mirela Simonovic wrote:
>>
>> On boot, enabling errata workarounds will be triggered by the boot CPU
>> from start_xen(). On CPU hotplug (non-boot scenario) this wo
Hi Julien,
On Wed, May 9, 2018 at 1:01 PM, Julien Grall wrote:
>
>
> On 09/05/18 11:10, Mirela Simonovic wrote:
>>
>> On Fri, Apr 27, 2018 at 5:12 PM, Julien Grall
>> wrote:
>>>
>>> On 27/04/18 15:38, Mirela Simonovic wrote:
>>>>
Hi Julien,
On Fri, Apr 27, 2018 at 5:12 PM, Julien Grall wrote:
>
>
> On 27/04/18 15:38, Mirela Simonovic wrote:
>>
>> Hi,
>>
>> On Fri, Apr 27, 2018 at 4:15 PM, Tim Deegan wrote:
>>>
>>> Hi,
>>>
>>> At 10:28 +0100 on 27 A
Hi Julien,
On Tue, May 8, 2018 at 4:14 PM, Julien Grall wrote:
>
>
> On 07/05/18 15:55, Mirela Simonovic wrote:
>>
>> Hi Julien,
>
>
> Hi Mirela,
>
>> On Mon, Apr 30, 2018 at 4:47 PM, Julien Grall
>> wrote:
>>>
>>> On 27/04/18
Hi Julien,
On Mon, Apr 30, 2018 at 5:58 PM, Julien Grall wrote:
> Hi,
>
>
> On 27/04/18 18:12, Mirela Simonovic wrote:
>>
>> When a CPU is hot-unplugged timer interrupts have to be released
>> in order to free the memory that was allocated when the interrupts
>&g
Hi Julien,
On Mon, Apr 30, 2018 at 4:47 PM, Julien Grall wrote:
> Hi Mirela,
>
>
> On 27/04/18 18:12, Mirela Simonovic wrote:
>>
>> In existing code the virtual paging for non-boot CPUs is setup only on
>> boot.
>> The setup is triggered from start_xen() afte
.
Signed-off-by: Mirela Simonovic
Reviewed-by: Stefano Stabellini
Acked-by: Julien Grall
---
CC: Stefano Stabellini
CC: Julien Grall
---
Changes in v2:
- Commit message fix (arm64 related change instead of arm)
- Add Stefano's reviewed-by
Changes in v3:
- Added Julien's acked-by
---
xe
already handled as 'read as zero'.
Signed-off-by: Mirela Simonovic
---
CC: Stefano Stabellini
CC: Julien Grall
---
Changes in v2:
- Write should be ignored only if the value to be written is zero
(in v1 the write was ignored regardless of the value)
Changes in v3:
- Print warning o
gioli
---
Mirela Simonovic (10):
xen/arm64: Added handling of the trapped access to OSLSR register
xen/arm: Ignore write to GICD_ISACTIVERn registers (vgic-v2)
xen/arm: Implement CPU_OFF PSCI call (physical interface)
xen/arm: Remove __initdata and __init to enable CPU hotplug
xen/arm: Setup vi
.
Signed-off-by: Mirela Simonovic
---
CC: Stefano Stabellini
CC: Julien Grall
---
Changes in v3:
-Use notifier to trigger remove_cpu_sibling_map() when the CPU dies.
---
xen/arch/arm/smpboot.c | 34 ++
1 file changed, 34 insertions(+)
diff --git a/xen/arch/arm
1 - 100 of 167 matches
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