Re: [Xen-devel] PCI Pass-through / Config Space emulation for ARM64

2018-07-18 Thread Manish Jaggi
On 07/18/2018 03:27 PM, Manish Jaggi wrote: On 07/02/2018 07:51 PM, Roger Pau Monné wrote: External Email On Mon, Jul 02, 2018 at 04:16:05PM +0530, Manish Jaggi wrote: Hi All, PCI-PT and PCI config space emulation have been in discussion for quite a long time. We had started some work

Re: [Xen-devel] PCI Pass-through / Config Space emulation for ARM64

2018-07-18 Thread Manish Jaggi
On 07/02/2018 07:51 PM, Roger Pau Monné wrote: External Email On Mon, Jul 02, 2018 at 04:16:05PM +0530, Manish Jaggi wrote: Hi All, PCI-PT and PCI config space emulation have been in discussion for quite a long time. We had started some work on this in past and in LEG-XEN but that didnt go

[Xen-devel] PCI Pass-through / Config Space emulation for ARM64

2018-07-02 Thread Manish Jaggi
Hi All, PCI-PT and PCI config space emulation have been in discussion for quite a long time. We had started some work on this in past and in LEG-XEN but that didnt go far and the group is closed. I believe that PCI-PT is a feature which would be suitable for not only for servers but for embe

Re: [Xen-devel] [v3 5/6] drivers/passthrough/arm: Refactor code for arm smmu drivers

2018-06-07 Thread Manish Jaggi
Hi Sameer, On 06/08/2018 05:17 AM, Sameer Goel wrote: Pull common defines for SMMU drives in a local header. Can add more detail in commit message? Signed-off-by: Sameer Goel --- xen/drivers/passthrough/arm/smmu-v3.c | 96 +--- xen/drivers/passthrough/arm/smmu.c| 104

Re: [Xen-devel] [PATCH v5 0/10] arm: more kconfig configurability and small default configs

2018-06-05 Thread Manish Jaggi
Hi Stefano, On 06/04/2018 10:53 PM, Stefano Stabellini wrote: Hi all, This patch series is the first step toward building a small certifiable Xen hypervisor for ARM boards. How much code size can be reduced ? any ballpark figure First, the series makes a few changes to allow disabling more

Re: [Xen-devel] [v2 4/6] xen/iommu: smmu-v3: Add Xen specific code to enable the ported driver

2018-06-02 Thread Manish Jaggi
On 06/02/2018 12:28 AM, Sameer Goel wrote: On 5/31/2018 11:16 PM, Manish Jaggi wrote: On 05/31/2018 09:27 PM, Sameer Goel wrote: On 5/30/2018 10:13 PM, Manish Jaggi wrote: On 05/31/2018 04:31 AM, Sameer Goel wrote: + +static int arm_smmu_iommu_domain_init(struct domain *d) Where is

Re: [Xen-devel] [v2 4/6] xen/iommu: smmu-v3: Add Xen specific code to enable the ported driver

2018-05-31 Thread Manish Jaggi
On 05/31/2018 09:27 PM, Sameer Goel wrote: On 5/30/2018 10:13 PM, Manish Jaggi wrote: On 05/31/2018 04:31 AM, Sameer Goel wrote: + +static int arm_smmu_iommu_domain_init(struct domain *d) Where is iommu_domain initialized? The function does not use a iommu_domain * variable Please check

Re: [Xen-devel] [v2 4/6] xen/iommu: smmu-v3: Add Xen specific code to enable the ported driver

2018-05-30 Thread Manish Jaggi
On 05/31/2018 04:31 AM, Sameer Goel wrote: + +static int arm_smmu_iommu_domain_init(struct domain *d) Where is iommu_domain initialized? The function does not use a iommu_domain * variable Please check iommu.c 2 levels up. In this function do you see iommu_domain getting allocated or initial

Re: [Xen-devel] [v2 4/6] xen/iommu: smmu-v3: Add Xen specific code to enable the ported driver

2018-05-30 Thread Manish Jaggi
On 05/31/2018 01:16 AM, Sameer Goel wrote: Manish, I'll take another look at the variable names. I might not have enough time :). On 05/23/2018 10:48 PM, Manish Jaggi wrote: Hi Sameer, General Comment, please use appropriate variable names for XXX_domain structures in code which i

[Xen-devel] [PATCH v3 17/17] arm64: if trapping a read-from-write-only GICv3 access inject undef exception in guest

2018-05-27 Thread Manish Jaggi
assume the worse and gracefully handle the case. Signed-off-by: Manish Jaggi diff --git a/xen/arch/arm/arm64/vgic-v3-sr.c b/xen/arch/arm/arm64/vgic-v3-sr.c index ac39eb5e1d..1b36b104bc 100644 --- a/xen/arch/arm/arm64/vgic-v3-sr.c +++ b/xen/arch/arm/arm64/vgic-v3-sr.c @@ -792,6 +792,

[Xen-devel] [PATCH v3 15/17] arm: Hook workaround handler from traps.c based on Cavium workaround_30115

2018-05-27 Thread Manish Jaggi
From: Manish Jaggi Function vgic_v3_handle_cpuif_access is called from do_trap_guest_sync if ARM64_WORKAROUND_CAVIUM_30115 capability is found. A flag skip_hyp_tail is introduced in struct cpu_info. This flag is used to skip leave_hypervisor_tail when enter_hypervisor_head is not invoked

[Xen-devel] [PATCH v3 12/17] arm64: vgic-v3: Add misc Group-0 handlers

2018-05-27 Thread Manish Jaggi
This patch is ported to xen from linux commit: eab0b2dc4f6f34147e3d10da49ab8032e15dbea0 A number of Group-0 registers can be handled by the same accessors as that of Group-1, so let's add the required system register encodings and catch them in the dispatching function. Signed-off-by: M

[Xen-devel] [PATCH v3 16/17] arm64: if trapping a write-to-read-only GICv3 access inject Undef exception in guest

2018-05-27 Thread Manish Jaggi
the worse and gracefully handle the case. Signed-off-by: Manish Jaggi diff --git a/xen/arch/arm/arm64/vgic-v3-sr.c b/xen/arch/arm/arm64/vgic-v3-sr.c index 27f5139dcb..ac39eb5e1d 100644 --- a/xen/arch/arm/arm64/vgic-v3-sr.c +++ b/xen/arch/arm/arm64/vgic-v3-sr.c @@ -782,6 +782,

[Xen-devel] [PATCH v3 13/17] arm64: cputype: Add MIDR values for Cavium ThunderX1 CPU family

2018-05-27 Thread Manish Jaggi
Add MIDR values for Cavium ThunderX1 SoC family: ThunderX1, 81XX, 83XX. This patch copies the below defines as is from linux kernel code. arch/arm64/include/asm/cputype.h Signed-off-by: Manish Jaggi diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h index 222a02dd99

[Xen-devel] [PATCH v3 00/17] arm64: Mediate access to GICv3 sysregs at EL2

2018-05-27 Thread Manish Jaggi
0115 which will auto enable workaround Manish Jaggi (17): arm: Placeholder code to handle guest GICv3 sysreg accesses at EL2 arm64: vgic-v3: Add ICV_BPR1_EL1 handler arm64: vgic-v3: Add ICV_IGRPEN1_EL1 handler arm64: vgic-v3: Add accessors for the ICH_APxRn_EL2 registers Expose ich_read/w

[Xen-devel] [PATCH v3 09/17] arm64: vgic-v3: Add ICV_BPR0_EL1 handler

2018-05-27 Thread Manish Jaggi
This patch is ported to xen from linux commit: 423de85a98c2b50715a0784a74f6124fbc0b1548 Add a handler for reading/writing the guest's view of the ICC_BPR0_EL1 register, which is located in the ICH_VMCR_EL2.BPR0 field. Signed-off-by: Manish Jaggi diff --git a/xen/arch/arm/arm64/vgic-v3-s

[Xen-devel] [PATCH v3 05/17] Expose ich_read/write_lr in vgic-v3-sr.c

2018-05-27 Thread Manish Jaggi
From: Manish Jaggi gicv3_ich_read/write_lr functions are duplicated in vgic-v3-sr.c This is done to make the file independent of the xen vgic code for handling the errata. Both the functions in the patch are static, so this patch needs subsequent patches to compile without error (unused

[Xen-devel] [PATCH v3 10/17] arm64: vgic-v3: Add ICV_IGRPEN0_EL1 handler

2018-05-27 Thread Manish Jaggi
This patch is ported to xen from linux commit: fbc48a0011deb3d51cb657ca9c0f9083f41c0665 Add a handler for reading/writing the guest's view of the ICC_IGRPEN0_EL1 register, which is located in the ICH_VMCR_EL2.VENG0 field. Signed-off-by: Manish Jaggi diff --git a/xen/arch/arm/arm64/vgic-v3

[Xen-devel] [PATCH v3 07/17] arm64: vgic-v3: Add ICV_EOIR1_EL1 handler

2018-05-27 Thread Manish Jaggi
This patch is ported to xen from linux commit b6f49035b4bf6e2709f2a5fed3107f5438c1fd02 Add a handler for writing the guest's view of the ICC_EOIR1_EL1 register. This involves dropping the priority of the interrupt, and deactivating it if required (EOImode == 0). Signed-off-by : Manish

[Xen-devel] [PATCH v3 08/17] arm64: vgic-v3: Add ICV_HPPIR1_EL1 handler

2018-05-27 Thread Manish Jaggi
lable interrupt. Signed-off-by: Manish Jaggi diff --git a/xen/arch/arm/arm64/vgic-v3-sr.c b/xen/arch/arm/arm64/vgic-v3-sr.c index 2192547cc4..c067278499 100644 --- a/xen/arch/arm/arm64/vgic-v3-sr.c +++ b/xen/arch/arm/arm64/vgic-v3-sr.c @@ -593,6 +593,27 @@ static void vgic_v3_write_eoir(s

[Xen-devel] [PATCH v3 03/17] arm64: vgic-v3: Add ICV_IGRPEN1_EL1 handler

2018-05-27 Thread Manish Jaggi
This patch is ported to xen from linux commit: f8b630bc542e0368886ae193d3519c832b270359 KVM: arm64: vgic-v3: Add ICV_IGRPEN1_EL1 handler Add a handler for reading/writing the guest's view of ICC_IGRPEN1_EL1 register, which is located in the ICH_VMCR_EL2.VENG1 field. Signed-off-by: Manish

[Xen-devel] [PATCH v3 14/17] arm64: Add config for Cavium Thunder erratum 30115

2018-05-27 Thread Manish Jaggi
: 690a341577f9adf2c275ababe0dcefe91898bbf0 arm64: Add workaround for Cavium Thunder erratum 30115 Signed-off-by: Manish Jaggi diff --git a/docs/misc/arm/silicon-errata.txt b/docs/misc/arm/silicon-errata.txt index c9854c39f4..a2546d4bb5 100644 --- a/docs/misc/arm/silicon-errata.txt +++ b/docs/misc/arm/silicon-errata.txt

[Xen-devel] [PATCH v3 02/17] arm64: vgic-v3: Add ICV_BPR1_EL1 handler

2018-05-27 Thread Manish Jaggi
bitfield extraction) Since the macro is a dependency both are merged in a single patch Add a handler for reading/writing the guest's view of the ICC_BPR1_EL1 register, which is located in the ICH_VMCR_EL2.BPR1 field. Signed-off-by: Manish Jaggi diff --git a/xen/arch/arm/arm64/vgic-v3-sr.c

[Xen-devel] [PATCH v3 01/17] arm: Placeholder code to handle guest GICv3 sysreg accesses at EL2

2018-05-27 Thread Manish Jaggi
From: Manish Jaggi The errata will require emulation of GIC virtual CPU interface in Xen. Because the hypervisor will update its internal state of the vGIC, we want to avoid messing up with it. So the errata is handled separately from the rest of the hypervisor. New file vgic-v3-sr.c is added

[Xen-devel] [PATCH v3 11/17] arm64: vgic-v3: Add ICV_AP1Rn_EL1 handler

2018-05-27 Thread Manish Jaggi
This patch is a xen port of linux commit f9e7449c780f688bf61a13dfa8c344afeb4ad6e0. Add a handler for reading/writing the guest's view of the ICV_AP1Rn_EL1 registers. We just map them to the corresponding ICH_AP(1)Rn_EL2 registers. Signed-off-by: Manish Jaggi diff --git a/xen/arch/arm/

[Xen-devel] [PATCH v3 06/17] arm64: Add ICV_IAR1_EL1 handler

2018-05-27 Thread Manish Jaggi
g the interrupt and setting the group priority as active. Signed-off-by: Manish Jaggi diff --git a/xen/arch/arm/arm64/vgic-v3-sr.c b/xen/arch/arm/arm64/vgic-v3-sr.c index 8e9318d959..1b47351bbb 100644 --- a/xen/arch/arm/arm64/vgic-v3-sr.c +++ b/xen/arch/arm/arm64/vgic-v3-sr.c @@ -25,8 +25,17 @@ #in

[Xen-devel] [PATCH v3 04/17] arm64: vgic-v3: Add accessors for the ICH_APxRn_EL2 registers

2018-05-27 Thread Manish Jaggi
parameter. This patch only has accessors, it does not modify the vgic code. Signed-off-by: Manish Jaggi diff --git a/xen/arch/arm/arm64/vgic-v3-sr.c b/xen/arch/arm/arm64/vgic-v3-sr.c index b49c53d1c5..eea087902c 100644 --- a/xen/arch/arm/arm64/vgic-v3-sr.c +++ b/xen/arch/arm/arm64/vgic-v3-sr.c @@ -3

Re: [Xen-devel] [v2 4/6] xen/iommu: smmu-v3: Add Xen specific code to enable the ported driver

2018-05-24 Thread Manish Jaggi
On 05/25/2018 01:59 AM, Sameer Goel wrote: On 05/23/2018 10:48 PM, Manish Jaggi wrote: Hi Sameer, General Comment, please use appropriate variable names for XXX_domain structures in code which is xen specific. I thought that we had discussed this before on one of the RFCs. Yes and no one

Re: [Xen-devel] [v2 4/6] xen/iommu: smmu-v3: Add Xen specific code to enable the ported driver

2018-05-23 Thread Manish Jaggi
Hi Sameer, General Comment, please use appropriate variable names for XXX_domain structures in code which is xen specific. On 05/24/2018 06:16 AM, Sameer Goel wrote: This driver follows an approach similar to smmu driver. The intent here is to reuse as much Linux code as possible. - Glue cod

Re: [Xen-devel] [PATCH 5/7] xen/iommu: smmu-v3: Add Xen specific code to enable the ported driver

2018-05-09 Thread Manish Jaggi
On 04/19/2018 04:24 PM, Manish Jaggi wrote: Sorry for top posting, is someone working on the comments on this patch? -Manish If no one is working this code anymore, I would like to pick it up and continue maintaining it. Is it fine with all? -Regards Manish On 03/10/2018 11:23 PM

Re: [Xen-devel] [PATCH 5/7] xen/iommu: smmu-v3: Add Xen specific code to enable the ported driver

2018-04-19 Thread Manish Jaggi
Sorry for top posting, is someone working on the comments on this patch? -Manish On 03/10/2018 11:23 PM, Manish Jaggi wrote: Hi Sameer, On 02/09/2018 08:40 AM, Sameer Goel wrote: This driver follows an approach similar to smmu driver. The intent here is to reuse as much Linux code as

Re: [Xen-devel] [PATCH v2 07/17] arm64: vgic-v3: Add ICV_EOIR1_EL1 handler

2018-04-06 Thread Manish Jaggi
On 04/05/2018 03:10 PM, Julien Grall wrote: Hi, On 02/04/18 12:17, Manish Jaggi wrote: On 04/02/2018 04:33 PM, Manish Jaggi wrote: On 03/27/2018 03:48 PM, Marc Zyngier wrote: On 27/03/18 10:07, Manish Jaggi wrote: This patch is ported to xen from linux commit

Re: [Xen-devel] [PATCH v2 07/17] arm64: vgic-v3: Add ICV_EOIR1_EL1 handler

2018-04-02 Thread Manish Jaggi
On 04/02/2018 04:33 PM, Manish Jaggi wrote: On 03/27/2018 03:48 PM, Marc Zyngier wrote: On 27/03/18 10:07, Manish Jaggi wrote: This patch is ported to xen from linux commit b6f49035b4bf6e2709f2a5fed3107f5438c1fd02 KVM: arm64: vgic-v3: Add ICV_EOIR1_EL1 handler Add a handler for writing the

Re: [Xen-devel] [PATCH v2 07/17] arm64: vgic-v3: Add ICV_EOIR1_EL1 handler

2018-04-02 Thread Manish Jaggi
On 03/27/2018 03:48 PM, Marc Zyngier wrote: On 27/03/18 10:07, Manish Jaggi wrote: This patch is ported to xen from linux commit b6f49035b4bf6e2709f2a5fed3107f5438c1fd02 KVM: arm64: vgic-v3: Add ICV_EOIR1_EL1 handler Add a handler for writing the guest's view of the ICC_EOIR1_EL1 reg

Re: [Xen-devel] [PATCH resend 02/13] acpi: arm: query estimated size of hardware domain's IORT.

2018-03-28 Thread Manish Jaggi
Hi Julien, On 03/21/2018 03:42 PM, Julien Grall wrote: Title: Please drop the full stop. On 03/13/2018 03:20 PM, mja...@caviumnetworks.com wrote: ... +    struct rid_devid_map *rmap; I am sorry but I still don't see any comment about my comment on the previous version. For reminder: "A

Re: [Xen-devel] [PATCH v2 02/17] arm64: vgic-v3: Add ICV_BPR1_EL1 handler

2018-03-27 Thread Manish Jaggi
On 03/27/2018 05:08 PM, Marc Zyngier wrote: On 27/03/18 12:27, Manish Jaggi wrote: On 03/27/2018 04:55 PM, Marc Zyngier wrote: On 27/03/18 12:15, Manish Jaggi wrote: On 03/27/2018 04:41 PM, Marc Zyngier wrote: On 27/03/18 12:07, Manish Jaggi wrote: On 03/27/2018 04:35 PM, Marc Zyngier

Re: [Xen-devel] [PATCH v2 01/17] arm: Placeholder for handling Group0/1 traps

2018-03-27 Thread Manish Jaggi
On 03/28/2018 06:18 AM, Julien Grall wrote: Hi, Sorry for the formatting. On Wed, 28 Mar 2018, 04:18 Stefano Stabellini, <mailto:sstabell...@kernel.org>> wrote: On Tue, 27 Mar 2018, Marc Zyngier wrote: > On 27/03/18 11:10, Manish Jaggi wrote: > > > &g

Re: [Xen-devel] [PATCH v2 02/17] arm64: vgic-v3: Add ICV_BPR1_EL1 handler

2018-03-27 Thread Manish Jaggi
On 03/27/2018 04:55 PM, Marc Zyngier wrote: On 27/03/18 12:15, Manish Jaggi wrote: On 03/27/2018 04:41 PM, Marc Zyngier wrote: On 27/03/18 12:07, Manish Jaggi wrote: On 03/27/2018 04:35 PM, Marc Zyngier wrote: On 27/03/18 11:56, Manish Jaggi wrote: On 03/27/2018 04:15 PM, Marc Zyngier

Re: [Xen-devel] [PATCH v2 02/17] arm64: vgic-v3: Add ICV_BPR1_EL1 handler

2018-03-27 Thread Manish Jaggi
On 03/27/2018 04:41 PM, Marc Zyngier wrote: On 27/03/18 12:07, Manish Jaggi wrote: On 03/27/2018 04:35 PM, Marc Zyngier wrote: On 27/03/18 11:56, Manish Jaggi wrote: On 03/27/2018 04:15 PM, Marc Zyngier wrote: On 27/03/18 11:35, Manish Jaggi wrote: On 03/27/2018 04:00 PM, Marc Zyngier

Re: [Xen-devel] [PATCH v2 02/17] arm64: vgic-v3: Add ICV_BPR1_EL1 handler

2018-03-27 Thread Manish Jaggi
On 03/27/2018 04:35 PM, Marc Zyngier wrote: On 27/03/18 11:56, Manish Jaggi wrote: On 03/27/2018 04:15 PM, Marc Zyngier wrote: On 27/03/18 11:35, Manish Jaggi wrote: On 03/27/2018 04:00 PM, Marc Zyngier wrote: On 27/03/18 10:07, Manish Jaggi wrote: This patch is ported to xen from linux

Re: [Xen-devel] [PATCH v2 09/17] arm64: vgic-v3: Add ICV_HPPIR1_EL1 handler

2018-03-27 Thread Manish Jaggi
On 03/27/2018 04:26 PM, Marc Zyngier wrote: On 27/03/18 10:07, Manish Jaggi wrote: This patch is ported from linux to xen commit: 2724c11a1df4b22ee966c04809ea0e808f66b04e (KVM: arm64: vgic-v3: Add ICV_HPPIR1_EL1 handler) Add a handler for reading the guest's view of the ICV_HPPIR

Re: [Xen-devel] [PATCH v2 12/17] arm64: vgic-v3: Add misc Group-0 handlers

2018-03-27 Thread Manish Jaggi
On 03/27/2018 04:28 PM, Marc Zyngier wrote: On 27/03/18 10:07, Manish Jaggi wrote: This patch is ported to xen from linux commit: eab0b2dc4f6f34147e3d10da49ab8032e15dbea0 (KVM: arm64: vgic-v3: Add misc Group-0 handlers) A number of Group-0 registers can be handled by the same accessors as

Re: [Xen-devel] [PATCH v2 02/17] arm64: vgic-v3: Add ICV_BPR1_EL1 handler

2018-03-27 Thread Manish Jaggi
On 03/27/2018 04:15 PM, Marc Zyngier wrote: On 27/03/18 11:35, Manish Jaggi wrote: On 03/27/2018 04:00 PM, Marc Zyngier wrote: On 27/03/18 10:07, Manish Jaggi wrote: This patch is ported to xen from linux commit d70c7b31a60f2458f35c226131f2a01a7a98b6cf KVM: arm64: vgic-v3: Add ICV_BPR1_EL1

Re: [Xen-devel] [PATCH v2 02/17] arm64: vgic-v3: Add ICV_BPR1_EL1 handler

2018-03-27 Thread Manish Jaggi
On 03/27/2018 04:00 PM, Marc Zyngier wrote: On 27/03/18 10:07, Manish Jaggi wrote: This patch is ported to xen from linux commit d70c7b31a60f2458f35c226131f2a01a7a98b6cf KVM: arm64: vgic-v3: Add ICV_BPR1_EL1 handler Add a handler for reading/writing the guest's view of the ICC_BPR

Re: [Xen-devel] [PATCH v2 01/17] arm: Placeholder for handling Group0/1 traps

2018-03-27 Thread Manish Jaggi
On 03/27/2018 03:31 PM, Marc Zyngier wrote: On 27/03/18 10:07, Manish Jaggi wrote: The errata will require to emulate the GIC virtual CPU interface in Xen. Because the hypervisor will update its internal state of the vGIC, we want to avoid messing up with it. So the errata is handled

[Xen-devel] [PATCH v2 17/17] arm64: if trapping a read-from-write-only GICv3 access inject undef exception in guest

2018-03-27 Thread Manish Jaggi
assume the worse and gracefully handle the case. Signed-off-by: Manish Jaggi --- xen/arch/arm/arm64/vgic-v3-sr.c | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/xen/arch/arm/arm64/vgic-v3-sr.c b/xen/arch/arm/arm64/vgic-v3-sr.c index 14276a4c92..d5dc8168c8 100644 --- a/xe

[Xen-devel] [PATCH v2 14/17] arm64: Add config for Cavium Thunder erratum 30115

2018-03-27 Thread Manish Jaggi
: 690a341577f9adf2c275ababe0dcefe91898bbf0 arm64: Add workaround for Cavium Thunder erratum 30115 Signed-off-by: Manish Jaggi --- docs/misc/arm/silicon-errata.txt | 1 + xen/arch/arm/Kconfig | 11 +++ xen/arch/arm/cpuerrata.c | 21 + xen/include/asm-arm/cpuerrata.h | 1

[Xen-devel] [PATCH v2 08/17] arm64: vgic-v3: Add ICV_AP1Rn_EL1 handler

2018-03-27 Thread Manish Jaggi
calls vreg_emulate_apxrN which has a if (hsr.sysreg.read) and based on that calls read and write functions. This code placement is slight different from linux code, which calls read/write functions from within switch case. Signed-off-by: Manish Jaggi --- xen/arch/arm/arm64/vgic-v3-sr.c

[Xen-devel] [PATCH v2 09/17] arm64: vgic-v3: Add ICV_HPPIR1_EL1 handler

2018-03-27 Thread Manish Jaggi
lable interrupt. Signed-off-by: Manish Jaggi --- xen/arch/arm/arm64/vgic-v3-sr.c | 31 +++ xen/include/asm-arm/arm64/sysregs.h | 1 + 2 files changed, 32 insertions(+) diff --git a/xen/arch/arm/arm64/vgic-v3-sr.c b/xen/arch/arm/arm64/vgic-v3-sr.c index c67e7

[Xen-devel] [PATCH v2 12/17] arm64: vgic-v3: Add misc Group-0 handlers

2018-03-27 Thread Manish Jaggi
n the dispatching function. Signed-off-by: Manish Jaggi --- xen/arch/arm/arm64/vgic-v3-sr.c | 7 +++ xen/include/asm-arm/arm64/sysregs.h | 4 2 files changed, 11 insertions(+) diff --git a/xen/arch/arm/arm64/vgic-v3-sr.c b/xen/arch/arm/arm64/vgic-v3-sr.c index d854b1070d..20119

[Xen-devel] [PATCH v2 16/17] arm64: if trapping a write-to-read-only GICv3 access inject Undef exception in guest

2018-03-27 Thread Manish Jaggi
the worse and gracefully handle the case. Signed-off-by: Manish Jaggi --- xen/arch/arm/arm64/vgic-v3-sr.c | 10 -- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/arm64/vgic-v3-sr.c b/xen/arch/arm/arm64/vgic-v3-sr.c index 201194c713..14276a4c92 100644 --- a/xe

[Xen-devel] [PATCH v2 13/17] arm64: cputype: Add MIDR values for Cavium ThunderX1 CPU family

2018-03-27 Thread Manish Jaggi
Add MIDR values for Cavium ThunderX1 SoC family: ThunderX1, 81XX, 83XX. This patch copies the below defines as is from linux kernel code. arch/arm64/include/asm/cputype.h Signed-off-by: Manish Jaggi --- xen/include/asm-arm/processor.h | 9 + 1 file changed, 9 insertions(+) diff --git

[Xen-devel] [PATCH v2 15/17] arm: Hook workaround handler from traps.c based on Cavium workaround_30115

2018-03-27 Thread Manish Jaggi
andleave_hypervisor_tail are invoked in sync, if one is not called other one should be skipped, otherwise guest vGIC state be out-of-date. Signed-off-by: Manish Jaggi --- xen/arch/arm/arm64/Makefile | 1 + xen/arch/arm/traps.c | 31 +++ xen/include/asm-arm

[Xen-devel] [PATCH v2 10/17] arm64: vgic-v3: Add ICV_BPR0_EL1 handler

2018-03-27 Thread Manish Jaggi
This patch is ported to xen from linux commit: 423de85a98c2b50715a0784a74f6124fbc0b1548 (KVM: arm64: vgic-v3: Add ICV_BPR0_EL1 handler) Add a handler for reading/writing the guest's view of the ICC_BPR0_EL1 register, which is located in the ICH_VMCR_EL2.BPR0 field. Signed-off-by: Manish

[Xen-devel] [PATCH v2 11/17] arm64: vgic-v3: Add ICV_IGRPEN0_EL1 handler

2018-03-27 Thread Manish Jaggi
This patch is ported to xen from linux commit: fbc48a0011deb3d51cb657ca9c0f9083f41c0665 (KVM: arm64: vgic-v3: Add ICV_IGNREN0_EL1 handler) Add a handler for reading/writing the guest's view of the ICC_IGRPEN0_EL1 register, which is located in the ICH_VMCR_EL2.VENG0 field. Signed-off-by: M

[Xen-devel] [PATCH v2 03/17] arm64: vgic-v3: Add ICV_IGRPEN1_EL1 handler

2018-03-27 Thread Manish Jaggi
This patch is ported to xen from linux commit: f8b630bc542e0368886ae193d3519c832b270359 KVM: arm64: vgic-v3: Add ICV_IGRPEN1_EL1 handler Add a handler for reading/writing the guest's view of ICC_IGRPEN1_EL1 register, which is located in the ICH_VMCR_EL2.VENG1 field. Signed-off-by: Manish

[Xen-devel] [PATCH v2 04/17] arm64: Add accessors for the ICH_APxRn_EL2 registers

2018-03-27 Thread Manish Jaggi
parameter. This patch only has accessors, it does not modify the vgic code. Signed-off-by: Manish Jaggi --- xen/arch/arm/arm64/vgic-v3-sr.c | 93 + 1 file changed, 93 insertions(+) diff --git a/xen/arch/arm/arm64/vgic-v3-sr.c b/xen/arch/arm/arm64/vgic-v3-

[Xen-devel] [PATCH v2 01/17] arm: Placeholder for handling Group0/1 traps

2018-03-27 Thread Manish Jaggi
trap and emulate code for group0 / group1 registers. Workaround for cavium Errata 30115 needs this emulation code. vgic_v3_handle_cpuif_access would be called from do_trap_guest_sync in subsequent patches based on errata macros. Signed-off-by: Manish Jaggi --- xen/arch/arm/arm64/vgic-v3-sr.c | 60

[Xen-devel] [PATCH v2 07/17] arm64: vgic-v3: Add ICV_EOIR1_EL1 handler

2018-03-27 Thread Manish Jaggi
uired (EOImode == 0). Signed-off-by : Manish Jaggi --- xen/arch/arm/arm64/vgic-v3-sr.c | 136 xen/include/asm-arm/arm64/sysregs.h | 1 + xen/include/asm-arm/gic_v3_defs.h | 4 ++ 3 files changed, 141 insertions(+) diff --git a/xen/arch/arm/arm64/vgic-v3

[Xen-devel] [PATCH v2 00/17] arm64: Mediate access to GICv3 sysregs at EL2

2018-03-27 Thread Manish Jaggi
anges from RFC - Added commit information on ported patches from linux - Added skip_hyp_tail to control calling leave_hypervisor_tail - Added CAVIUM_CONFIG_ERRATUM_30115 which will auto enable workaround Manish Jaggi (17): arm: Placeholder for handling Group0/1 traps arm64: vgic-v3

[Xen-devel] [PATCH v2 02/17] arm64: vgic-v3: Add ICV_BPR1_EL1 handler

2018-03-27 Thread Manish Jaggi
This patch is ported to xen from linux commit d70c7b31a60f2458f35c226131f2a01a7a98b6cf KVM: arm64: vgic-v3: Add ICV_BPR1_EL1 handler Add a handler for reading/writing the guest's view of the ICC_BPR1_EL1 register, which is located in the ICH_VMCR_EL2.BPR1 field. Signed-off-by: Manish

[Xen-devel] [PATCH v2 06/17] arm64: Add ICV_IAR1_EL1 handler

2018-03-27 Thread Manish Jaggi
h PMR and the active group priority, activating the interrupt and setting the group priority as active. Signed-off-by: Manish Jaggi --- xen/arch/arm/arm64/vgic-v3-sr.c | 194 xen/include/asm-arm/arm64/sysregs.h | 1 + xen/include/asm-arm/gic_v3_defs.h

[Xen-devel] [PATCH v2 05/17] Expose ich_read/write_lr in vgic-v3-sr.c

2018-03-27 Thread Manish Jaggi
: Manish Jaggi --- xen/arch/arm/arm64/vgic-v3-sr.c | 83 + 1 file changed, 83 insertions(+) diff --git a/xen/arch/arm/arm64/vgic-v3-sr.c b/xen/arch/arm/arm64/vgic-v3-sr.c index 48346ed628..fc5246539e 100644 --- a/xen/arch/arm/arm64/vgic-v3-sr.c +++ b/xen/arch

Re: [Xen-devel] [PATCH v1 06/15] arm64: Add accessors for the ICH_APxRn_EL2 registers

2018-03-26 Thread Manish Jaggi
.html -manish On 03/16/2018 05:28 PM, Manish Jaggi wrote: This patch is ported to xen from linux commit 63000dd8006dc987db31ba670edc23142ea91e01 As we're about to access the Active Priority registers a lot more, let's define accessors that take the register number as a parameter. This

Re: [Xen-devel] [PATCH v1 04/15] arm64: vgic-v3: Add ICV_BPR1_EL1 handler

2018-03-26 Thread Manish Jaggi
On 03/21/2018 01:41 PM, Julien Grall wrote: Hi Manish, On 03/16/2018 11:58 AM, Manish Jaggi wrote: This patch is ported to xen from linux commit d70c7b31a60f2458f35c226131f2a01a7a98b6cf Add a handler for reading/writing the guest's view of the ICC_BPR1_EL1 register, which is located i

Re: [Xen-devel] [PATCH v1 05/15] arm64: vgic-v3: Add ICV_IGRPEN1_EL1 handler

2018-03-26 Thread Manish Jaggi
Hi Julien, On 03/21/2018 02:08 PM, Julien Grall wrote: On 03/16/2018 11:58 AM, Manish Jaggi wrote: This patch is ported to xen from linux commit: f8b630bc542e0368886ae193d3519c832b270359 Add a handler for reading/writing the guest's view of the ICC_IGRPEN1_EL1 The wrapping looks

Re: [Xen-devel] [PATCH v1 00/15] arm64: Mediate access to GICv3 sysregs at EL2

2018-03-25 Thread Manish Jaggi
On 03/23/2018 12:28 PM, Julien Grall wrote: (Sorry for the formatting) On 23 Mar 2018 14:46, "Manish Jaggi" <mailto:mja...@caviumnetworks.com>> wrote: On 03/21/2018 03:26 PM, Julien Grall wrote: Hi Manish, On 03/21/2018 09:38 AM, Manish Jaggi wrote

Re: [Xen-devel] [PATCH v1 00/15] arm64: Mediate access to GICv3 sysregs at EL2

2018-03-22 Thread Manish Jaggi
On 03/21/2018 03:26 PM, Julien Grall wrote: Hi Manish, On 03/21/2018 09:38 AM, Manish Jaggi wrote: On 03/21/2018 02:15 PM, Julien Grall wrote: On 03/21/2018 04:58 AM, Manish Jaggi wrote: Hi Julien, On 03/20/2018 01:16 PM, Julien Grall wrote: On 03/16/2018 11:58 AM, Manish Jaggi

Re: [Xen-devel] [PATCH resend 03/13] acpi: arm: Code to generate Hardware Domains IORT

2018-03-22 Thread Manish Jaggi
On 03/23/2018 06:58 AM, Julien Grall wrote: Hi Manish, On 03/13/2018 03:20 PM, mja...@caviumnetworks.com wrote: From: Manish Jaggi Structure of Hardware domain's (hwdom) IORT hwdom's IORT will only have PCIRC nodes and ITS group nodes in the following order. SMMU nodes as they

Re: [Xen-devel] [PATCH v1 00/15] arm64: Mediate access to GICv3 sysregs at EL2

2018-03-21 Thread Manish Jaggi
On 03/21/2018 02:15 PM, Julien Grall wrote: On 03/21/2018 04:58 AM, Manish Jaggi wrote: Hi Julien, On 03/20/2018 01:16 PM, Julien Grall wrote: On 03/16/2018 11:58 AM, Manish Jaggi wrote: This patchset is a Xen port of Marc's patchset. arm64: KVM: Mediate access to GICv3 sysregs a

Re: [Xen-devel] [PATCH resend 01/13] acpi: arm: API: Populate/query rid-devid rid-sid map.

2018-03-21 Thread Manish Jaggi
On 03/21/2018 02:59 PM, Julien Grall wrote: Hi Manish, Hi Julien, On 03/13/2018 03:20 PM, mja...@caviumnetworks.com wrote: From: Manish Jaggi IORT has a hierarchical structure containing PCIRC nodes, IORT nodes and SMMU nodes. Each node has with it an array of ids and a mapping which maps

Re: [Xen-devel] [PATCH v1 02/15] arm64: Add config for Cavium Thunder erratum 30115

2018-03-20 Thread Manish Jaggi
On 03/20/2018 01:13 PM, Julien Grall wrote: Hi, On 03/16/2018 11:58 AM, Manish Jaggi wrote: Some Cavium Thunder CPUs suffer a problem where a Xen guest may inadvertently cause the host kernel to quit receiving interrupts. This patch adds CONFIG_CAVIUM_ERRATUM_30115. Subsequent patches will

Re: [Xen-devel] [PATCH v1 00/15] arm64: Mediate access to GICv3 sysregs at EL2

2018-03-20 Thread Manish Jaggi
Hi Julien, On 03/20/2018 01:16 PM, Julien Grall wrote: On 03/16/2018 11:58 AM, Manish Jaggi wrote: This patchset is a Xen port of Marc's patchset. arm64: KVM: Mediate access to GICv3 sysregs at EL2 [1] The current RFC patchset is a subset of [1], as it handleing only Group1 traps as

[Xen-devel] [PATCH v1 15/15] Enable Group0/1 Traps by default for Cavium ThunderX1

2018-03-16 Thread Manish Jaggi
Enable trapping for Group0/1 register access when CONFIG_CAVIUM_ERRATUM_30115 is enabled. Signed-off-by: Manish Jaggi diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index 473e26111f..6ffed6a634 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -43,6 +43,7

[Xen-devel] [PATCH v1 14/15] arm64: vgic-v3: Add ICV_AP(0/1)Rn_EL1 handler

2018-03-16 Thread Manish Jaggi
This patch is a xen port of linux commit f9e7449c780f688bf61a13dfa8c344afeb4ad6e0. Add a handler for reading/writing the guest's view of the ICV_AP1Rn_EL1 registers. We just map them to the corresponding ICH_AP(0/1)Rn_EL2 registers. Signed-off-by: Manish Jaggi diff --git a/xen/arch/arm/

[Xen-devel] [PATCH v1 13/15] arm64: vgic-v3: Add misc Group-0 handlers

2018-03-16 Thread Manish Jaggi
This patch is ported to xen from linux commit: eab0b2dc4f6f34147e3d10da49ab8032e15dbea0 A number of Group-0 registers can be handled by the same accessors as that of Group-1, so let's add the required system register encodings and catch them in the dispatching function. Signed-off-by: M

[Xen-devel] [PATCH v1 00/15] arm64: Mediate access to GICv3 sysregs at EL2

2018-03-16 Thread Manish Jaggi
lling leave_hypervisor_tail - Added CAVIUM_CONFIG_ERRATUM_30115 which will auto enable workaround Manish Jaggi (15): arm64: cputype: Add MIDR values for Cavium ThunderX1 CPU family arm64: Add config for Cavium Thunder erratum 30115 arm: Placeholder for handling Group0/1 traps for Cavium Erratum

[Xen-devel] [PATCH v1 10/15] arm64: vgic-v3: Add ICV_HPPIR1_EL1 handler

2018-03-16 Thread Manish Jaggi
lable interrupt. Signed-off-by: Manish Jaggi diff --git a/xen/arch/arm/arm64/vgic-v3-sr.c b/xen/arch/arm/arm64/vgic-v3-sr.c index 35bad3953f..537e164062 100644 --- a/xen/arch/arm/arm64/vgic-v3-sr.c +++ b/xen/arch/arm/arm64/vgic-v3-sr.c @@ -611,6 +611,26 @@ void handle_eoi(struct cpu_user_regs *regs

[Xen-devel] [PATCH v1 09/15] arm64: vgic-v3: Add ICV_EOIR1_EL1 handler

2018-03-16 Thread Manish Jaggi
This patch is ported to xen from linux commit b6f49035b4bf6e2709f2a5fed3107f5438c1fd02 Add a handler for writing the guest's view of the ICC_EOIR1_EL1 register. This involves dropping the priority of the interrupt, and deactivating it if required (EOImode == 0). Signed-off-by : Manish

[Xen-devel] [PATCH v1 05/15] arm64: vgic-v3: Add ICV_IGRPEN1_EL1 handler

2018-03-16 Thread Manish Jaggi
This patch is ported to xen from linux commit: f8b630bc542e0368886ae193d3519c832b270359 Add a handler for reading/writing the guest's view of the ICC_IGRPEN1_EL1 register, which is located in the ICH_VMCR_EL2.VENG1 field. Signed-off-by: Manish Jaggi diff --git a/xen/arch/arm/arm64/vgic-v3

[Xen-devel] [PATCH v1 03/15] arm: Placeholder for handling Group0/1 traps for Cavium Erratum 30115

2018-03-16 Thread Manish Jaggi
one should be skipped, otherwise guest vGIC state be out-of-date. Signed-off-by: Manish Jaggi diff --git a/xen/arch/arm/arm64/Makefile b/xen/arch/arm/arm64/Makefile index 718fe44455..02cc115239 100644 --- a/xen/arch/arm/arm64/Makefile +++ b/xen/arch/arm/arm64/Makefile @@ -11,3 +11,4 @@ obj-y

[Xen-devel] [PATCH v1 07/15] Expose ich_read/write_lr in vgic-v3-sr.c

2018-03-16 Thread Manish Jaggi
gicv3_ich_read/write_lr functions are duplicated in vgic-v3-sr.c This is done to make the file independent of the xen vgic code for handling the errata. Signed-off-by: Manish Jaggi diff --git a/xen/arch/arm/arm64/vgic-v3-sr.c b/xen/arch/arm/arm64/vgic-v3-sr.c index 1aaade40dc..93ac6f03a9 100644

[Xen-devel] [PATCH v1 08/15] arm64: Add ICV_IAR1_EL1 handler

2018-03-16 Thread Manish Jaggi
g the interrupt and setting the group priority as active. Signed-off-by: Manish Jaggi diff --git a/xen/arch/arm/arm64/vgic-v3-sr.c b/xen/arch/arm/arm64/vgic-v3-sr.c index 93ac6f03a9..8af943b37a 100644 --- a/xen/arch/arm/arm64/vgic-v3-sr.c +++ b/xen/arch/arm/arm64/vgic-v3-sr.c @@ -21,8 +21,18 @@ #in

[Xen-devel] [PATCH v1 11/15] arm64: vgic-v3: Add ICV_BPR0_EL1 handler

2018-03-16 Thread Manish Jaggi
This patch is ported to xen from linux commit: 423de85a98c2b50715a0784a74f6124fbc0b1548 Add a handler for reading/writing the guest's view of the ICC_BPR0_EL1 register, which is located in the ICH_VMCR_EL2.BPR0 field. Signed-off-by: Manish Jaggi diff --git a/xen/arch/arm/arm64/vgic-v3-s

[Xen-devel] [PATCH v1 12/15] arm64: vgic-v3: Add ICV_IGNREN0_EL1 handler

2018-03-16 Thread Manish Jaggi
This patch is ported to xen from linux commit: fbc48a0011deb3d51cb657ca9c0f9083f41c0665 Add a handler for reading/writing the guest's view of the ICC_IGRPEN0_EL1 register, which is located in the ICH_VMCR_EL2.VENG0 field. Signed-off-by: Manish Jaggi diff --git a/xen/arch/arm/arm64/vgic-v3

[Xen-devel] [PATCH v1 04/15] arm64: vgic-v3: Add ICV_BPR1_EL1 handler

2018-03-16 Thread Manish Jaggi
This patch is ported to xen from linux commit d70c7b31a60f2458f35c226131f2a01a7a98b6cf Add a handler for reading/writing the guest's view of the ICC_BPR1_EL1 register, which is located in the ICH_VMCR_EL2.BPR1 field. Signed-off-by: Manish Jaggi diff --git a/xen/arch/arm/arm64/vgic-v3-s

[Xen-devel] [PATCH v1 06/15] arm64: Add accessors for the ICH_APxRn_EL2 registers

2018-03-16 Thread Manish Jaggi
ister trap handlers Signed-off-by: Manish Jaggi diff --git a/xen/arch/arm/arm64/vgic-v3-sr.c b/xen/arch/arm/arm64/vgic-v3-sr.c index 114d5107a9..1aaade40dc 100644 --- a/xen/arch/arm/arm64/vgic-v3-sr.c +++ b/xen/arch/arm/arm64/vgic-v3-sr.c @@ -114,6 +114,98 @@ void handle_igrpen1(struct cpu_user_regs

[Xen-devel] [PATCH v1 02/15] arm64: Add config for Cavium Thunder erratum 30115

2018-03-16 Thread Manish Jaggi
Some Cavium Thunder CPUs suffer a problem where a Xen guest may inadvertently cause the host kernel to quit receiving interrupts. This patch adds CONFIG_CAVIUM_ERRATUM_30115. Subsequent patches will provide workaround. Signed-off-by: Manish Jaggi diff --git a/docs/misc/arm/silicon-errata.txt b

[Xen-devel] [PATCH v1 01/15] arm64: cputype: Add MIDR values for Cavium ThunderX1 CPU family

2018-03-16 Thread Manish Jaggi
Add MIDR values for Cavium ThunderX1 SoC family. ThunderX1, 81XX, 83XX. Signed-off-by: Manish Jaggi diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h index 65eb1071e1..62ad244785 100644 --- a/xen/include/asm-arm/processor.h +++ b/xen/include/asm-arm/processor.h

Re: [Xen-devel] [PATCH 01/12] arm:Kconfig Rename menu text

2018-03-14 Thread Manish Jaggi
Hi Julien, On 03/13/2018 05:45 PM, Julien Grall wrote: Hi, On 12/03/18 12:42, mja...@caviumnetworks.com wrote: From: Manish Jaggi Rename the menu text to Errata Workarounds. Subsequent patches will add config options for SoC specific erratas. Well, your SoC is an Arm SoC, right? So what

Re: [Xen-devel] [PATCH 00/13] acpi: arm: Add IORT Support

2018-03-13 Thread Manish Jaggi
correct e-mail address. sent to Julien Grall this time. Cheers, On 12/03/18 07:49, mja...@caviumnetworks.com wrote: From: Manish Jaggi This patch aims to add the support of IORT in Xen. Below is the list of major components which this patchset provides. a. Add support for parsing the IORT b

Re: [Xen-devel] [PATCH 5/7] xen/iommu: smmu-v3: Add Xen specific code to enable the ported driver

2018-03-11 Thread Manish Jaggi
On 10 March 2018 at 23:23, Manish Jaggi wrote: > Hi Sameer, > > > > On 02/09/2018 08:40 AM, Sameer Goel wrote: >> >> This driver follows an approach similar to smmu driver. The intent here >> is to reuse as much Linux code as possible. >> - Glue code has

Re: [Xen-devel] [PATCH 5/7] xen/iommu: smmu-v3: Add Xen specific code to enable the ported driver

2018-03-10 Thread Manish Jaggi
Hi Sameer, On 02/09/2018 08:40 AM, Sameer Goel wrote: This driver follows an approach similar to smmu driver. The intent here is to reuse as much Linux code as possible. - Glue code has been introduced to bridge the API calls. - Called Linux functions from the Xen IOMMU function calls. - Xen mo

Re: [Xen-devel] [RFC 06/11] fwnode xen spacific changes

2018-03-06 Thread Manish Jaggi
Hi Julien, On 01/19/2018 12:21 AM, Julien Grall wrote: diff --git a/xen/include/asm-arm/device.h b/xen/include/asm-arm/device.h index 6734ae8efd..f78482ca0c 100644 --- a/xen/include/asm-arm/device.h +++ b/xen/include/asm-arm/device.h @@ -6,6 +6,8 @@   enum device_type   {   DEV_DT, +    DEV

Re: [Xen-devel] [RFC 06/11] fwnode xen spacific changes

2018-03-06 Thread Manish Jaggi
Hi Julien, On 01/19/2018 12:21 AM, Julien Grall wrote: diff --git a/xen/include/asm-arm/device.h b/xen/include/asm-arm/device.h index 6734ae8efd..f78482ca0c 100644 --- a/xen/include/asm-arm/device.h +++ b/xen/include/asm-arm/device.h @@ -6,6 +6,8 @@   enum device_type   {   DEV_DT, +    DEV

Re: [Xen-devel] [RFC 06/11] fwnode xen spacific changes

2018-03-06 Thread Manish Jaggi
On 01/19/2018 12:21 AM, Julien Grall wrote: Hi Manish, Please use scripts/get_maintainers.pl to CC relevant maintainers. I have done it for you this time. Title: s/spacific/specific/ On 02/01/18 09:28, manish.ja...@linaro.org wrote: From: Manish Jaggi Merge few more changes from linux

Re: [Xen-devel] [PATCH 0/7] SMMUv3 driver

2018-03-04 Thread Manish Jaggi
On 03/01/2018 08:05 PM, Julien Grall wrote: Hi, On 09/02/18 03:10, Sameer Goel wrote: This patch set adds support for the SMMUv3 driver. This is a continuation on a RFCv4.[1] The IORT support came from [2]. This RFC has some conflicting defines that have to be addressed by introducing the l

Re: [Xen-devel] [RFC PATCH 02/10] arm64: Add hook to handle guest GICv3 sysreg accesses

2018-02-25 Thread Manish Jaggi
On 02/26/2018 12:12 PM, Manish Jaggi wrote: On 02/01/2018 04:24 PM, Julien Grall wrote: Hi Manish, On 01/02/18 08:51, Manish Jaggi wrote: On 01/25/2018 11:37 PM, Julien Grall wrote: Hi, I forgot to mention one thing about the placement of do_fixup_vgic_errata. On 16/01/18 15:42, mja

Re: [Xen-devel] [RFC PATCH 02/10] arm64: Add hook to handle guest GICv3 sysreg accesses

2018-02-25 Thread Manish Jaggi
On 02/01/2018 04:24 PM, Julien Grall wrote: Hi Manish, On 01/02/18 08:51, Manish Jaggi wrote: On 01/25/2018 11:37 PM, Julien Grall wrote: Hi, I forgot to mention one thing about the placement of do_fixup_vgic_errata. On 16/01/18 15:42, mja...@caviumnetworks.com wrote: diff --git a/xen

Re: [Xen-devel] [RFC PATCH 01/10] Add CONFIG_VGIC_ERRATA

2018-02-21 Thread Manish Jaggi
Hi Julien, On 01/25/2018 07:18 PM, Julien Grall wrote: Hi Manish, On 16/01/18 15:42, mja...@caviumnetworks.com wrote: From: Manish Jaggi Add a config option to enable VGIC Errata Code in Xen. Platforms which do not have this errta can compile out this feature. s/errta/errata/ Signed

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