On 13.01.2025 18:11, Oleksii Kurochko wrote:
> On 1/8/25 4:21 PM, Jan Beulich wrote:
>> On 23.12.2024 13:55, Oleksii Kurochko wrote:
>>> +struct riscv_isa_ext_data {
>>> +const unsigned int id;
>>> +const char *name;
>>> +};
>> This is odd - why would the id be const, but not the name? Thus
On 13.01.2025 18:18, Oleksii Kurochko wrote:
> I would like to kindly ask the x86 maintainers for clarification on why
> this patch series was not merged.
v1 of this patch was submitted on Dec 19, when patch submission deadline
was Nov 29.
Jan
Both GCC and Clang support -fstack-protector feature, which add stack
canaries to functions where stack corruption is possible. This patch
makes general preparations to enable this feature on different
supported architectures:
- Added CONFIG_HAS_STACK_PROTECTOR option so each architecture
can
Both GCC and Clang support -fstack-protector feature, which add stack
canaries to functions where stack corruption is possible. This series
makes possible to use this feature in Xen. I tested this on ARM64 and
it is working as intended. Tested both with GCC and Clang.
It is hard to enable this fea
Enable previously added CONFIG_STACK_PROTECTOR feature for ARM
platform. We initialize stack protector very early, in head.S using
boot_stack_chk_guard_setup. This ensures that all C code from the very
beginning can use stack protector.
Signed-off-by: Volodymyr Babchuk
---
In v4:
- setup.c does
This patch is preparation for making stack protector
configurable. First step is to remove -fno-stack-protector flag from
EMBEDDED_EXTRA_CFLAGS so separate components (Hypervisor in this case)
can enable/disable this feature by themselves.
Signed-off-by: Volodymyr Babchuk
Reviewed-by: Jan Beulich
Stack protector is meant to be enabled on all architectures, but
currently it is tested (and enabled) only on ARM, so mention it in ARM
section.
Signed-off-by: Volodymyr Babchuk
---
CHANGELOG.md | 1 +
1 file changed, 1 insertion(+)
diff --git a/CHANGELOG.md b/CHANGELOG.md
index 8507e6556a..62e
Some devices, like discrete GPU of amd, support resizable bar
capability, but vpci of Xen doesn't support this feature, so
they fail to resize bars and then cause probing failure.
According to PCIe spec, each bar that supports resizing has
two registers, PCI_REBAR_CAP and PCI_REBAR_CTRL. So, add
h
On Mon, Jan 13, 2025 at 11:18:57AM +0100, Roger Pau Monné wrote:
> On Fri, Jan 10, 2025 at 04:21:29PM -0600, Bjorn Helgaas wrote:
> > On Fri, Jan 10, 2025 at 03:01:48PM +0100, Roger Pau Monne wrote:
> > > The PCI segment value is limited to 16 bits, however there are buses like
> > > VMD
> > > tha
On Mon, Jan 13, 2025 at 11:25:58AM +0100, Roger Pau Monné wrote:
> On Fri, Jan 10, 2025 at 04:30:57PM -0600, Bjorn Helgaas wrote:
> > On Fri, Jan 10, 2025 at 03:01:50PM +0100, Roger Pau Monne wrote:
> > > Setting pci_msi_ignore_mask inhibits the toggling of the mask bit for
> > > both MSI
> > > an
Solaris 11.4 tries to access this MSR on some Intel platforms without properly
setting up a proper #GP handler, which leads to a immediate crash.
Emulate the access of this MSR by giving it a legal value (all values set to
default, as defined by Intel SDM "RAPL Interfaces").
Fixes: 84e848fd7a1 ('
On Mon, Jan 13, 2025 at 05:07:55PM +0100, Marek Marczykowski-Górecki wrote:
> On Fri, Sep 13, 2024 at 09:59:06AM +0200, Roger Pau Monne wrote:
> > Allow setting the used wallclock from the command line. When the option is
> > set
> > to a value different than `auto` the probing is bypassed and th
On 1/13/25 06:17, Mykyta Poturai wrote:
> On 09.11.23 20:27, Stewart Hildebrand wrote:
>> This series introduces SMMU handling for PCIe passthrough on ARM. These
>> patches
>> should be able to be upstreamed independently from the vPCI series [1]. See
>> [2]
>> for notes about test cases.
>>
>> [
On 1/9/25 4:25 PM, Tamas K Lengyel wrote:
On Thu, Jan 9, 2025 at 9:30 AM Oleksii Kurochko
wrote:
On 1/2/25 6:13 PM, Petr Beneš wrote:
From: Petr Beneš
Changes since v2:
- Reset entry->pw in all cases in p2m_set_entry, except for p2m_access_r_pw
Changes since v1:
- Added signed-off-by tag
On 1/8/25 4:21 PM, Jan Beulich wrote:
On 23.12.2024 13:55, Oleksii Kurochko wrote:
--- /dev/null
+++ b/xen/arch/riscv/cpufeature.c
@@ -0,0 +1,466 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Taken for Linux kernel v6.12-rc3 and modified by
+ * Oleksii Kurochko:
+ *
+ * - Drop uncondi
On Mon, Jan 13, 2025 at 05:45:20PM +0100, Roger Pau Monné wrote:
> On Mon, Jan 13, 2025 at 08:11:19AM -0700, Keith Busch wrote:
> > On Mon, Jan 13, 2025 at 11:03:58AM +0100, Roger Pau Monné wrote:
> > >
> > > Hm, OK, but isn't the limit 80 columns according to the kernel coding
> > > style (Docume
On Mon, Jan 13, 2025 at 08:11:19AM -0700, Keith Busch wrote:
> On Mon, Jan 13, 2025 at 11:03:58AM +0100, Roger Pau Monné wrote:
> >
> > Hm, OK, but isn't the limit 80 columns according to the kernel coding
> > style (Documentation/process/coding-style.rst)?
>
> That's the coding style. The commit
On Fri, Sep 13, 2024 at 09:59:06AM +0200, Roger Pau Monne wrote:
> Allow setting the used wallclock from the command line. When the option is
> set
> to a value different than `auto` the probing is bypassed and the selected
> implementation is used (as long as it's available).
>
> The `xen` and
On Mon, Jan 13, 2025 at 11:03:58AM +0100, Roger Pau Monné wrote:
>
> Hm, OK, but isn't the limit 80 columns according to the kernel coding
> style (Documentation/process/coding-style.rst)?
That's the coding style. The commit message style is described in a
different doc:
https://docs.kernel.o
On Wed, Jan 8, 2025 at 1:23 PM Andrew Cooper wrote:
> Seeing as this is the only issue, I'm happy to fix on commit?
Fine by me!
P.
On 01/01/2025 7:03 pm, Maximilian Engelhardt wrote:
> On Montag, 30. Dezember 2024 23:28:42 CET Maximilian Engelhardt wrote:
>> On Montag, 30. Dezember 2024 22:38:24 CET Andrew Cooper wrote:
>>> On 30/12/2024 9:00 pm, Maximilian Engelhardt wrote:
Use the solution described in [1] to replace th
On 10/01/2025 9:19 pm, Maximilian Engelhardt wrote:
> Not having ppc and riscv included in DOC_ARCHES causes "multiple
> definitions of ..." message on documentation build, similar to the
> example shown below:
>
> include/public/arch-ppc.h:91: multiple definitions of Typedef
> vcpu_guest_core_regs
On 09.11.23 20:27, Stewart Hildebrand wrote:
> This series introduces SMMU handling for PCIe passthrough on ARM. These
> patches
> should be able to be upstreamed independently from the vPCI series [1]. See
> [2]
> for notes about test cases.
>
> [1] https://lists.xenproject.org/archives/html/xe
On 10.01.25 02:27, Stefano Stabellini wrote:
> On Wed, 8 Jan 2025, Mykyta Poturai wrote:
>> From: Oleksandr Andrushchenko
>>
>> There are number of ITS implementations exist which are different from
>> the base one which have number of functionalities defined as is
>> "IMPLEMENTATION DEFINED", e.g
On Fri, Jan 10, 2025 at 04:30:57PM -0600, Bjorn Helgaas wrote:
> Match subject line style again.
>
> On Fri, Jan 10, 2025 at 03:01:50PM +0100, Roger Pau Monne wrote:
> > Setting pci_msi_ignore_mask inhibits the toggling of the mask bit for both
> > MSI
> > and MSI-X entries globally, regardless o
On Fri, Jan 10, 2025 at 04:21:29PM -0600, Bjorn Helgaas wrote:
> On Fri, Jan 10, 2025 at 03:01:48PM +0100, Roger Pau Monne wrote:
> > The PCI segment value is limited to 16 bits, however there are buses like
> > VMD
> > that fake being part of the PCI topology by adding segment with a number
> > o
On Mon, Jan 13, 2025 at 08:17:23AM +0100, Jan Beulich wrote:
> On 10.01.2025 15:01, Roger Pau Monne wrote:
> > The PCI segment value is limited to 16 bits, however there are buses like
> > VMD
> > that fake being part of the PCI topology by adding segment with a number
> > outside the scope of the
On Fri, Jan 10, 2025 at 10:02:00PM -0700, Jonathan Derrick wrote:
> Hi Bjorn,
>
> On 1/10/25 3:25 PM, Bjorn Helgaas wrote:
> > Match historical subject line style for prefix and capitalization:
> >
> >PCI: vmd: Set devices to D0 before enabling PM L1 Substates
> >PCI: vmd: Add DID 8086:B0
On Fri, Jan 10, 2025 at 04:25:25PM -0600, Bjorn Helgaas wrote:
> Match historical subject line style for prefix and capitalization:
>
> PCI: vmd: Set devices to D0 before enabling PM L1 Substates
> PCI: vmd: Add DID 8086:B06F and 8086:B60B for Intel client SKUs
> PCI: vmd: Fix indentation is
On Thu, Jan 09, 2025 at 03:57:07PM +0100, Thomas Zimmermann wrote:
> Call drm_mode_size_dumb() to compute dumb-buffer scanline pitch and
> buffer size. The hardware requires the scnaline pitch to be a multiple
> of 32 pixels. Therefore compute the byte size of 32 pixels in the given
> color mode an
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