On 29.11.2024 02:49, Volodymyr Babchuk wrote:
> Currently, even if we are using clang as a C compiler, we still use
> GNU binutils. This patch adds new option "llvm" that allows to use
> linker, objcopy and all other tools from LLVM project. As LLVM tools
> use different approach for cross-compilat
On 29.11.2024 02:49, Volodymyr Babchuk wrote:
> Before this change, compiler would generate symbol that points right
> past .rodata.str section. While GNU ld handles this just fine, LLVM ld
> will complain:
>
> ld.lld: error: common/device-tree/device-tree.o:(.rodata.str): offset is
> outside the
This patch series addresses two main issues:
1. Some errors when using clang for aarch64 build
2. Unability to use clang for cross-compilation
While first problem has straightforward fix: add -march argument and
allow to use FP registers for vfg.c, second one is much trickier. I am
aware of the
vfp.c actually accesses VFP registers, so it can't be built with
-mgeneral-regs-only flag when using clang, as clang will complain
about this:
arch/arm/arm64/vfp.c:9:18: error: instruction requires: fp-armv8
9 | asm volatile("stp q0, q1, [%1, #16 * 0]\n\t"
|
Signed-off-by: Volodymyr
This variable can be used in cases when we need to remove certain
CFLAGS for particular object file. One such case is
-mgeneral-regs-only flags that should be omitted when we are building
an object file that uses not only general registers.
Signed-off-by: Volodymyr Babchuk
---
xen/Rules.mk | 2 +
Provide -target and -march explicitly when building with clang. This
makes cross-compilation much easier, because clang accept this
parameters regardless of host platform. Basically,
make XEN_TARGET_ARCH=arm64 clang=y llvm=y
will behave in the same way if building Xen on x86, or on arm64 or on
Before this change, compiler would generate symbol that points right
past .rodata.str section. While GNU ld handles this just fine, LLVM ld
will complain:
ld.lld: error: common/device-tree/device-tree.o:(.rodata.str): offset is
outside the section
Fix this issue by providing literal zero instead
Currently, even if we are using clang as a C compiler, we still use
GNU binutils. This patch adds new option "llvm" that allows to use
linker, objcopy and all other tools from LLVM project. As LLVM tools
use different approach for cross-compilation, we don't need
CROSS_COMPILE prefix in this case.
Consider also "Display controller" an IGD, not only "VGA compatible
controller". Specifically, IGD on Raptor Lake has 0x038000 class, not
0x03.
Signed-off-by: Marek Marczykowski-Górecki
---
tools/libs/light/libxl_pci.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tools
Hi Luca,
Sorry for the late answer.
On 26/11/2024 13:52, Luca Fancellu wrote:
On 26 Nov 2024, at 13:29, Jan Beulich wrote:
On 26.11.2024 14:25, Luca Fancellu wrote:
This reads better, thanks. Follow-on question: Is what is statically
configured for the heap guaranteed to never overlap wit
Hi Oleksii,
On 19/11/2024 14:55, Oleksii Kurochko wrote:
Rename the file containing uart_init() to enable reuse across other
architectures that utilize device trees or SPCR tables to locate UART
information.
After locating UART data, {acpi}_device_init() is called to initialize
the UART.
arm_ua
Hi,
On 16/11/2024 10:18, Julien Grall wrote:
On 14/11/2024 10:28, Luca Fancellu wrote:
There are some cases where the device tree exposes a memory range
in both /memreserve/ and reserved-memory node, in this case the
current code will stop Xen to boot since it will find that the
latter range is
Hi Jan,
On 26/11/2024 08:02, Jan Beulich wrote:
On 25.11.2024 23:17, Julien Grall wrote:
--- a/xen/arch/arm/include/asm/page.h
+++ b/xen/arch/arm/include/asm/page.h
@@ -144,6 +144,12 @@ extern size_t dcache_line_bytes;
#define copy_page(dp, sp) memcpy(dp, sp, PAGE_SIZE)
+#define clea
On Tue, Nov 26, 2024 at 12:19:41PM -0500, Jason Andryuk wrote:
> diff --git a/tools/xl/xl_vmcontrol.c b/tools/xl/xl_vmcontrol.c
> index c45d497c28..3160966972 100644
> --- a/tools/xl/xl_vmcontrol.c
> +++ b/tools/xl/xl_vmcontrol.c
> @@ -42,6 +42,16 @@ static void unpause_domain(uint32_t domid)
>
On Tue, Nov 26, 2024 at 12:19:40PM -0500, Jason Andryuk wrote:
> When a VM transitioned to LIBXL_SHUTDOWN_REASON_SUSPEND, the xl daemon
> was exiting as 0 = DOMAIN_RESTART_NONE "No domain restart".
> Later, when the VM actually shutdown, the missing xl daemon meant the
> domain wasn't cleaned up pr
On 28/11/2024 3:31 pm, James Dingwall wrote:
> Hi,
>
> We have reproducible issue with the current HEAD of the stable-4.18 branch
> which crashes a network driver domain and on some hardware subsequently
> results in a dom0 crash.
>
> `xl info` reports: free_memory : 39961, configuring a guest with
Hi,
We have reproducible issue with the current HEAD of the stable-4.18 branch
which crashes a network driver domain and on some hardware subsequently
results in a dom0 crash.
`xl info` reports: free_memory : 39961, configuring a guest with
memory = 39800 and starting it gives the log as below.
On 28/11/2024 1:28 pm, Jan Beulich wrote:
> Due to presumably a copy-and-paste mistake VPBROADCASTMB2Q was tested
> twice instead.
>
> Signed-off-by: Jan Beulich
Acked-by: Andrew Cooper
Due to presumably a copy-and-paste mistake VPBROADCASTMB2Q was tested
twice instead.
Signed-off-by: Jan Beulich
--- a/tools/tests/x86_emulator/predicates.c
+++ b/tools/tests/x86_emulator/predicates.c
@@ -1889,7 +1889,7 @@ static const struct evex {
{ { 0x39 }, 2, T, R, pfx_66, Wn, Ln }, /*
looks good
On Sat, Nov 16, 2024 at 12:32 AM Easwar Hariharan
wrote:
>
> Changes made with the following Coccinelle rules:
>
> @@ constant C; @@
>
> - msecs_to_jiffies(C * 1000)
> + secs_to_jiffies(C)
>
> @@ constant C; @@
>
> - msecs_to_jiffies(C * MSEC_PER_SEC)
> + secs_to_jiffies(C)
>
> Signed-
looks good
On Fri, Nov 15, 2024 at 11:35 PM Easwar Hariharan
wrote:
>
> Changes made with the following Coccinelle rules:
>
> @@ constant C; @@
>
> - msecs_to_jiffies(C * 1000)
> + secs_to_jiffies(C)
>
> @@ constant C; @@
>
> - msecs_to_jiffies(C * MSEC_PER_SEC)
> + secs_to_jiffies(C)
>
> Signed-
On 28.11.2024 12:57, Andrew Cooper wrote:
> On 28/11/2024 11:50 am, Jan Beulich wrote:
>> On 28.11.2024 12:10, Andrew Cooper wrote:
>>> On 28/11/2024 10:31 am, Jan Beulich wrote:
On 28.11.2024 01:47, Andrew Cooper wrote:
> Xen currently presents APIC_ESR to guests as a simple read/write re
On 19/11/2024 15:13, Carlo Nonato wrote:
>
>
> Add the "llc-colors" Device Tree attribute to express DomUs and Dom0less
NIT: s/attribute/property/
> color configurations.
>
> Based on original work from: Luca Miccio
>
> Signed-off-by: Carlo Nonato
> Signed-off-by: Marco Solieri
> Reviewe
On 28/11/2024 11:50 am, Jan Beulich wrote:
> On 28.11.2024 12:10, Andrew Cooper wrote:
>> On 28/11/2024 10:31 am, Jan Beulich wrote:
>>> On 28.11.2024 01:47, Andrew Cooper wrote:
Xen currently presents APIC_ESR to guests as a simple read/write register.
This is incorrect. The SDM st
On 19.11.2024 15:13, Carlo Nonato wrote:
> Add the cache coloring support for Xen physical space.
>
> Since Xen must be relocated to a new physical space, some relocation
> functionalities must be brought back:
> - the virtual address of the new space is taken from 0c18fb76323b
> ("xen/arm: Remo
On 28.11.2024 12:10, Andrew Cooper wrote:
> On 28/11/2024 10:31 am, Jan Beulich wrote:
>> On 28.11.2024 01:47, Andrew Cooper wrote:
>>> Xen currently presents APIC_ESR to guests as a simple read/write register.
>>>
>>> This is incorrect. The SDM states:
>>>
>>> The ESR is a write/read register.
On 19.11.2024 15:13, Carlo Nonato wrote:
> --- a/docs/misc/xen-command-line.pandoc
> +++ b/docs/misc/xen-command-line.pandoc
> @@ -270,6 +270,20 @@ and not running softirqs. Reduce this if softirqs are
> not being run frequently
> enough. Setting this to a high value may cause boot failure, parti
On 19/11/2024 15:13, Carlo Nonato wrote:
>
>
> Add a command line parameter to allow the user to set the coloring
> configuration for Dom0.
> A common configuration syntax for cache colors is introduced and
> documented.
> Take the opportunity to also add:
> - default configuration notion.
>
On 28/11/2024 10:31 am, Jan Beulich wrote:
> On 28.11.2024 01:47, Andrew Cooper wrote:
>> Xen currently presents APIC_ESR to guests as a simple read/write register.
>>
>> This is incorrect. The SDM states:
>>
>> The ESR is a write/read register. Before attempt to read from the ESR,
>> software
On 28.11.2024 12:01, Andrew Cooper wrote:
> On 28/11/2024 9:03 am, Roger Pau Monné wrote:
>> On Thu, Nov 28, 2024 at 12:47:36AM +, Andrew Cooper wrote:
>>> diff --git a/xen/arch/x86/hvm/vlapic.c b/xen/arch/x86/hvm/vlapic.c
>>> index 3363926b487b..98394ed26a52 100644
>>> --- a/xen/arch/x86/hvm/v
On 19.11.2024 15:13, Carlo Nonato wrote:
> PGC_static, PGC_extra and PGC_broken need to be preserved when assigning a
> page. Define a new macro that groups those flags and use it instead of or'ing
> every time.
>
> To make preserved flags even more meaningful, they are kept also when
> switching
On 28/11/2024 9:03 am, Roger Pau Monné wrote:
> On Thu, Nov 28, 2024 at 12:47:36AM +, Andrew Cooper wrote:
>> diff --git a/xen/arch/x86/hvm/vlapic.c b/xen/arch/x86/hvm/vlapic.c
>> index 3363926b487b..98394ed26a52 100644
>> --- a/xen/arch/x86/hvm/vlapic.c
>> +++ b/xen/arch/x86/hvm/vlapic.c
>> @@
On 28/11/2024 9:41 am, Jan Beulich wrote:
> On 27.11.2024 19:01, Andrew Cooper wrote:
>> On 27/11/2024 8:20 am, Jan Beulich wrote:
>>> On 26.11.2024 21:58, Andrew Cooper wrote:
--- a/xen/arch/x86/smpboot.c
+++ b/xen/arch/x86/smpboot.c
@@ -422,7 +422,7 @@ void asmlinkage start_seconda
On 28/11/2024 10:25 am, Roger Pau Monné wrote:
> On Thu, Nov 28, 2024 at 10:10:39AM +, Andrew Cooper wrote:
>> On 28/11/2024 9:26 am, Roger Pau Monné wrote:
>>> On Thu, Nov 28, 2024 at 12:47:37AM +, Andrew Cooper wrote:
With vlapic->hw.pending_esr held outside of the main regs page, it
On 19.11.2024 15:13, Carlo Nonato wrote:
> LLC coloring needs to know the last level cache layout in order to make the
> best use of it. This can be probed by inspecting the CLIDR_EL1 register,
> so the Last Level is defined as the last level visible by this register.
> Note that this excludes syst
On 19.11.2024 15:13, Carlo Nonato wrote:
> --- /dev/null
> +++ b/xen/include/xen/llc-coloring.h
> @@ -0,0 +1,37 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Last Level Cache (LLC) coloring common header
> + *
> + * Copyright (C) 2024, Advanced Micro Devices, Inc.
> + * Copyright (C
On 19/11/2024 15:13, Carlo Nonato wrote:
>
>
> Cache coloring requires Dom0 not to be direct-mapped because of its non
> contiguous mapping nature, so allocate_memory() is needed in this case.
> 8d2c3ab18cc1 ("arm/dom0less: put dom0less feature code in a separate module")
> moved allocate_memo
On 28.11.2024 01:47, Andrew Cooper wrote:
> Xen currently presents APIC_ESR to guests as a simple read/write register.
>
> This is incorrect. The SDM states:
>
> The ESR is a write/read register. Before attempt to read from the ESR,
> software should first write to it. (The value written doe
On Thu, Nov 28, 2024 at 10:10:39AM +, Andrew Cooper wrote:
> On 28/11/2024 9:26 am, Roger Pau Monné wrote:
> > On Thu, Nov 28, 2024 at 12:47:37AM +, Andrew Cooper wrote:
> >> With vlapic->hw.pending_esr held outside of the main regs page, it's much
> >> easier to use atomic operations.
> >>
On 28/11/2024 9:26 am, Roger Pau Monné wrote:
> On Thu, Nov 28, 2024 at 12:47:37AM +, Andrew Cooper wrote:
>> With vlapic->hw.pending_esr held outside of the main regs page, it's much
>> easier to use atomic operations.
>>
>> Use xchg() in vlapic_reg_write(), and *set_bit() in vlapic_error().
>
On 27.11.2024 19:01, Andrew Cooper wrote:
> On 27/11/2024 8:20 am, Jan Beulich wrote:
>> On 26.11.2024 21:58, Andrew Cooper wrote:
>>> --- a/xen/arch/x86/smpboot.c
>>> +++ b/xen/arch/x86/smpboot.c
>>> @@ -422,7 +422,7 @@ void asmlinkage start_secondary(void *unused)
>>> static int wakeup_secondary
On Thu, Nov 28, 2024 at 12:47:37AM +, Andrew Cooper wrote:
> With vlapic->hw.pending_esr held outside of the main regs page, it's much
> easier to use atomic operations.
>
> Use xchg() in vlapic_reg_write(), and *set_bit() in vlapic_error().
>
> The only interesting change is that vlapic_erro
On Wed, Nov 27, 2024 at 05:45:29PM +, Andrew Cooper wrote:
> On 27/11/2024 10:03 am, Javi Merino wrote:
> > On Tue, Nov 26, 2024 at 08:58:59PM +, Andrew Cooper wrote:
> >> The SDM instructs software to write 0 to ESR prior to reading it. However,
> >> due to an original Pentium erratum, mo
On Thu, Nov 28, 2024 at 12:47:36AM +, Andrew Cooper wrote:
> Xen currently presents APIC_ESR to guests as a simple read/write register.
>
> This is incorrect. The SDM states:
>
> The ESR is a write/read register. Before attempt to read from the ESR,
> software should first write to it. (
On 25.11.2024 16:06, Jan Beulich wrote:
> --- a/xen/arch/x86/x86_emulate/x86_emulate.c
> +++ b/xen/arch/x86/x86_emulate/x86_emulate.c
> @@ -7037,10 +7037,68 @@ x86_emulate(
> state->simd_size = simd_none;
> break;
>
> -case X86EMUL_OPC_F2(0x0f38, 0xf8): /* enqcmd r,m512 */
>
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