On Wed, 24 Jun 2015 16:26:44 -0400
Elena Ufimtseva wrote:
> On Wed, Jun 24, 2015 at 07:24:18PM +0100, Andrew Cooper wrote:
> > On 24/06/15 08:49, Jan Beulich wrote:
> > On 24.06.15 at 04:34, wrote:
> > >> On 06/23/2015 08:30 AM, Jan Beulich wrote:
> > >> On 22.06.15 at 18:37, wrote:
>
On Thu, 4 Dec 2014 17:35:59 +0100
Roger Pau Monné wrote:
> Hello,
>
> I've just stumbled upon this assert while testing PVH on different
> hardware. It was added in 7c4870 as a safe belt, but it turns out INS
> and OUTS go through handle_mmio. So using this instructions from a PVH
> guest basica
On Fri, 05 Dec 2014 14:06:53 +
"Jan Beulich" wrote:
> PVH guests are not supposed to access I/O ports they weren't given
> access to (there's nothing to handle emulation of such accesses).
>
> Reported-by: Roger Pau Monné
> Signed-off-by: Jan Beulich
> ---
> Note: Only compile tested so far
gp_fault, 0);
> }
> else
>
Good idea, and if needed:
Acked-by: Mukesh Rathor
thanks
Mukesh
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Call pv_cpuid for pvh cpuid intercept. Note, we modify
svm_vmexit_do_cpuid instead of the intercept switch because the guest
eip needs to be adjusted for pvh also.
Signed-off-by: Mukesh Rathor
---
xen/arch/x86/hvm/svm/svm.c | 24 ++--
1 file changed, 14 insertions(+), 10
PVH doesn't use apic emulation hence vlapic->regs ptr is not set for it.
Signed-off-by: Mukesh Rathor
---
xen/arch/x86/hvm/svm/svm.c | 25 ++---
1 file changed, 14 insertions(+), 11 deletions(-)
diff --git a/xen/arch/x86/hvm/svm/svm.c b/xen/arch/x86/hvm/svm/svm
Finally, enable pvh if the cpu supports NPT and svm decode.
Signed-off-by: Mukesh Rathor
---
xen/arch/x86/hvm/svm/svm.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/xen/arch/x86/hvm/svm/svm.c b/xen/arch/x86/hvm/svm/svm.c
index 4bb4ff2..8b27a76 100644
--- a/xen/arch/x86/hvm/svm/svm.c
PVH guest starts in Long 64bit paging mode. This patch modifies
construct_vmcb for that.
Signed-off-by: Mukesh Rathor
---
xen/arch/x86/hvm/svm/vmcb.c | 18 +++---
1 file changed, 15 insertions(+), 3 deletions(-)
diff --git a/xen/arch/x86/hvm/svm/vmcb.c b/xen/arch/x86/hvm/svm/vmcb.c
On AMD, MSR_AMD64_TSC_RATIO must be set for rdtsc instruction in guest
to properly read the cpu tsc. To that end, set tsc_khz in struct domain.
Signed-off-by: Mukesh Rathor
---
xen/arch/x86/time.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/xen/arch/x86/time.c b/xen/arch/x86/time.c
-by: Mukesh Rathor
---
xen/arch/x86/hvm/svm/svm.c | 20
1 file changed, 16 insertions(+), 4 deletions(-)
diff --git a/xen/arch/x86/hvm/svm/svm.c b/xen/arch/x86/hvm/svm/svm.c
index 4ff4a96..dac16f4 100644
--- a/xen/arch/x86/hvm/svm/svm.c
+++ b/xen/arch/x86/hvm/svm/svm.c
Hi Elena/Boris:
Actually, I forgot I had already made and tested AMD SVM and other changes
for domU support, please find the patches.
So the only thing remaining for AMD would be iommu support and SVM vmexit
for CR reads and writes which currently calls handle_mmio (which patch #3
attempted, bu
On Mon, 5 Jan 2015 15:35:27 +
Andrew Cooper wrote:
> On 05/01/15 15:16, Ian Campbell wrote:
> > On Fri, 2015-01-02 at 19:12 +, Andrew Cooper wrote:
> >> supervisor_mode_kernel was an x86_32-only feature which permitted
> >> a PV dom0 to run in ring 0, but at the expense of not being able
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