napshot SGX guest by either:
- Suspend guest before snapshot (s3-s5). This works for all guests but
requires user to manually susppend guest.
- Issue an hypercall to destroy guest's EPC in save_vm. This only works for
Linux and Windows but doesn't require user interve
, or
by PV ENCLS but it is really not necessary at this stage. And currently SGX
is only exposed to HAP HVM domain (we can add for shadow in the future).
SGX Launch Control is also exposed in CPU featureset for HVM domain. SGX
Launch Control depends on SGX.
Signed-off-by: Kai Huang
---
xen/include
ll 'struct epc_page' will
be in an array which is allocated during SGX initialization. Entire EPC is also
mapped to Xen's virtual address so that each EPC page's virtual address can be
calculated by base virtual address + offset.
Signed-off-by: Kai Huang
in guest, vcpu's virtual IA32_SGXLEPUBKEYHASHn
will be update to physical MSRs when vcpu is scheduled in.
Signed-off-by: Kai Huang
---
xen/arch/x86/hvm/vmx/sgx.c | 194 +
xen/arch/x86/hvm/vmx/vmx.c | 24 +
xen/include/asm-x86/cpuf
EPC is destroyed when power state goes to S3-S5. Emulate this behavior.
A new function s3_suspend is added to hvm_function_table for this purpose.
Signed-off-by: Kai Huang
---
xen/arch/x86/hvm/hvm.c| 3 +++
xen/arch/x86/hvm/vmx/vmx.c| 7 +++
xen/include/asm-x86/hvm/hvm.h | 3
scheduling, etc, as well), so currently only
one EPC is supported.
Dedicated files sgx.c and sgx.h are added (under vmx directory as SGX is Intel
specific) for bulk of above SGX detection code detection code, and for further
SGX code as well.
Signed-off-by: Kai Huang
---
xen/arch/x86/hvm/vm
om L2 guest,
we simply inject it to L1, otherwise the ENCLS VMEXIT is unexpected in L0
and we simply crash the domain.
Signed-off-by: Kai Huang
---
xen/arch/x86/hvm/vmx/vmx.c | 10 ++
xen/arch/x86/hvm/vmx/vvmx.c| 11 +++
xen/include/asm-x86/hvm/vmx/vmcs.h | 1 +
xen/in
VMX adds new bit to both exit_reason and GUEST_INTERRUPT_STATE to indicate
whether VMEXIT happens in Enclave. Several instructions are also invalid or
behave differently in enclave according to SDM. This patch handles those
cases.
Signed-off-by: Kai Huang
---
xen/arch/x86/hvm/vmx/vmx.c
lid. Used when domain
goes to S3-S5, or being destroyed.
- hvm_destroy_epc # destroy and free domain's EPC.
Signed-off-by: Kai Huang
---
xen/arch/x86/hvm/vmx/sgx.c | 315 +
xen/arch/x86/hvm/vmx/vmx.c | 3 +
xen/
If ENCLS VMEXIT is not present then we cannot support SGX virtualization.
This patch detects presence of ENCLS VMEXIT. A Xen boot boolean parameter
'sgx' is also added to manually enable/disable SGX.
Signed-off-by: Kai Huang
---
xen/arch/x86/hvm/vmx/vmcs.c| 17
e from toolstack via XEN_DOMCTL_set_cpuid,
so domain's EPC pages are also populated in XEN_DOMCTL_set_cpuid, after
receiving valid EPC base and size. Failure to populate EPC (such as there's
no enough free EPC pages) results in domain creation failure by making
XEN_DOMCTL_set_cpuid return er
Currently Xen only has non-cacheable version of ioremap. Although EPC is
reported as reserved memory in e820 but it can be mapped as cacheable. This
patch adds ioremap_cache (cacheable version of ioremap).
Signed-off-by: Kai Huang
---
xen/arch/x86/mm.c | 15 +--
xen/include/xen
A new 'p2m_epc' type is added for EPC mapping type. Two wrapper functions
set_epc_p2m_entry and clear_epc_p2m_entry are also added for further use.
Signed-off-by: Kai Huang
---
xen/arch/x86/mm/p2m-ept.c | 3 +++
xen/arch/x86/mm/p2m.c | 41
assed to xc_cpuid_apply_policy.
xc_cpuid_apply_policy is extended to support SGX CPUID. If hypervisor doesn't
report SGX feature in host type cpufeatureset, then using 'epc' parameter
results in domain creation failure as SGX cannot be supported.
Signed-off-by: Kai Huang
---
tools/libxc/inc
fo. EPC base and size are also added to
'xc_dom_image' in order to add EPC to e820 table. EPC base is calculated
internally.
Signed-off-by: Kai Huang
---
tools/libxc/include/xc_dom.h | 4
tools/libxl/libxl_create.c | 9 +
tools/libxl/libxl_dom.c | 30
On physical machine EPC is exposed in ACPI table via "INT0E0C". Although EPC
can be discovered by CPUID but Windows driver requires EPC to be exposed in
ACPI table as well. This patch exposes EPC in ACPI table.
Signed-off-by: Kai Huang
---
tools/firmware/hvmloader/ut
Since PML series were merged (but disabled by default) we have conducted lots of
PML tests (live migration, GUI display) and PML has been working fine, therefore
turn it on by default.
Signed-off-by: Kai Huang
Tested-by: Robert Hu
Tested-by: Xudong Hao
---
In case you might want some specific
On 11/27/2015 04:35 PM, Jan Beulich wrote:
On 27.11.15 at 08:57, wrote:
Since PML series were merged (but disabled by default) we have conducted lots of
PML tests (live migration, GUI display) and PML has been working fine, therefore
turn it on by default.
Well, I'm not really opposed, but i
Since PML series were merged (but disabled by default) we have conducted lots of
PML tests (live migration, GUI display) and PML has been working fine, therefore
turn it on by default.
Document of PML command line is adjusted accordingly as well.
Signed-off-by: Kai Huang
Tested-by: Robert Hu
, Kai Huang wrote:
Design
==
- PML feature is used globally
A new Xen boot parameter, say 'opt_enable_pml', will be introduced to
control PML feature detection, and PML feature will only be detected
if opt_enable_pml = 1. Once PML feature is detected, it will be used
for dirty loggi
On Thu, Mar 12, 2015 at 7:19 PM, Andrew Cooper
wrote:
> On 12/03/15 07:36, Kai Huang wrote:
>>
>>>>> It might also be nice to be able to enable or disable this feature
>>>>> with a sysctl call; but that's just a nice-to-have.
>>>> This fea
On 02/17/2015 06:19 PM, Jan Beulich wrote:
On 12.02.15 at 03:39, wrote:
On 02/11/2015 07:52 PM, Andrew Cooper wrote:
On 11/02/15 08:28, Kai Huang wrote:
Design
==
- PML feature is used globally
A new Xen boot parameter, say 'opt_enable_pml', will be introduced to
control P
On 03/24/2015 03:53 PM, Jan Beulich wrote:
On 24.03.15 at 07:42, wrote:
On 02/17/2015 06:19 PM, Jan Beulich wrote:
On 12.02.15 at 03:39, wrote:
On 02/11/2015 07:52 PM, Andrew Cooper wrote:
On 11/02/15 08:28, Kai Huang wrote:
Design
==
- PML feature is used globally
A new Xen boot
On 03/24/2015 04:14 PM, Jan Beulich wrote:
On 24.03.15 at 09:06, wrote:
On 03/24/2015 03:53 PM, Jan Beulich wrote:
The command line
option parsing is (and should be) independent of the chosen
default anyway, i.e. overrides in either direction should be
possible.
While the parse_ept_param
54fdb3..88a10f1 100644
--- a/tools/libxc/xc_domain_save.c
+++ b/tools/libxc/xc_domain_save.c
@@ -335,7 +335,12 @@ static int analysis_phase(xc_interface *xch, uint32_t
domid, struct save_ctx *ct
start = llgettimeofday();
+#define PML_TEST
+#ifdef PML_TEST
+for ( j
A top level EPT parameter "ept=" and a sub boolean "pml_enable" are
added to control PML. Other booleans can be further added for any other EPT
related features.
Signed-off-by: Kai Huang
---
xen/arch/x86/hvm/vmx/vmcs.c | 32
1 file ch
PML requires A/D bit support so enable it for further use.
Signed-off-by: Kai Huang
---
xen/arch/x86/hvm/vmx/vmcs.c| 1 +
xen/arch/x86/mm/p2m-ept.c | 8 +++-
xen/include/asm-x86/hvm/vmx/vmcs.h | 4 +++-
xen/include/asm-x86/hvm/vmx/vmx.h | 5 -
4 files changed, 15
The patch adds PML definition and feature detection. Note PML won't be detected
if PML is disabled from boot parameter. PML is also disabled in construct_vmcs,
as it will only be enabled when domain is switched to log dirty mode.
Signed-off-by: Kai Huang
---
xen/arch/x86/hvm/vmx/v
It's possible domain has already been in log-dirty mode when creating vcpu, in
which case we should enable PML for this vcpu if PML has been enabled for the
domain.
Signed-off-by: Kai Huang
---
xen/arch/x86/hvm/vmx/vmx.c | 24
1 file changed, 24 insertions(+)
;t have to be initialized to zero explicitly as both
vcpu and domain structure are zero-ed when they are created.
Signed-off-by: Kai Huang
---
xen/include/asm-x86/hvm/vmx/vmcs.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/xen/include/asm-x86/hvm/vmx/vmcs.h
b/xen/include/asm-x86/hvm
It's possible domain still remains in log-dirty mode when it is about to be
destroyed, in which case we should manually disable PML for it.
Signed-off-by: Kai Huang
---
xen/arch/x86/hvm/vmx/vmx.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen
This patch adds help functions to enable/disable PML, and flush PML buffer for
single vcpu and particular domain for further use.
Signed-off-by: Kai Huang
---
xen/arch/x86/hvm/vmx/vmcs.c| 190 +
xen/include/asm-x86/hvm/vmx/vmcs.h | 9 ++
2 files
We need to flush PML buffer when it's full.
Signed-off-by: Kai Huang
---
xen/arch/x86/hvm/vmx/vmx.c | 4
1 file changed, 4 insertions(+)
diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c
index e1c55ce..453bcc5 100644
--- a/xen/arch/x86/hvm/vmx/vmx.c
+++ b/xen/arc
gging, as PML works globally at entire valid EPT table.
Signed-off-by: Kai Huang
---
xen/arch/x86/mm/hap/hap.c | 15 --
xen/arch/x86/mm/p2m-ept.c | 73 +++
2 files changed, 80 insertions(+), 8 deletions(-)
diff --git a/xen/arch/x86/mm/hap/hap.c
switching back to normal mode respectively.
Flushing PML buffer callback will be called from paging layer when flushing PML
buffer manually.
Signed-off-by: Kai Huang
---
xen/arch/x86/mm/hap/hap.c | 16 +++-
xen/arch/x86/mm/p2m.c | 36
On 03/28/2015 05:26 AM, Andrew Cooper wrote:
On 27/03/15 02:35, Kai Huang wrote:
Hi all,
This patch series adds PML support to Xen. Please kindly help to review it.
Overall this looks like a very good series, and it is particularly
helpful given the level of commenting.
Which platforms is
On 03/28/2015 04:38 AM, Andrew Cooper wrote:
On 27/03/15 02:35, Kai Huang wrote:
PML requires A/D bit support so enable it for further use.
Signed-off-by: Kai Huang
---
xen/arch/x86/hvm/vmx/vmcs.c| 1 +
xen/arch/x86/mm/p2m-ept.c | 8 +++-
xen/include/asm-x86/hvm/vmx
On 03/28/2015 04:42 AM, Andrew Cooper wrote:
On 27/03/15 02:35, Kai Huang wrote:
A top level EPT parameter "ept=" and a sub boolean "pml_enable" are
added to control PML. Other booleans can be further added for any other EPT
related features.
Signed-off-by: Kai Huang
Pl
On 03/28/2015 04:46 AM, Andrew Cooper wrote:
On 27/03/15 02:35, Kai Huang wrote:
The patch adds PML definition and feature detection. Note PML won't be detected
if PML is disabled from boot parameter. PML is also disabled in construct_vmcs,
as it will only be enabled when domain is swi
On 03/28/2015 04:48 AM, Andrew Cooper wrote:
On 27/03/15 02:35, Kai Huang wrote:
A new 4K page pointer is added to arch_vmx_struct as PML buffer for vcpu. And a
new 'status' field is added to vmx_domain to indicate whether PML is enabled for
the domain or not. The 'status
On 03/28/2015 05:09 AM, Andrew Cooper wrote:
On 27/03/15 02:35, Kai Huang wrote:
This patch adds help functions to enable/disable PML, and flush PML buffer for
single vcpu and particular domain for further use.
Signed-off-by: Kai Huang
---
xen/arch/x86/hvm/vmx/vmcs.c| 190
On 03/28/2015 05:12 AM, Andrew Cooper wrote:
On 27/03/15 02:35, Kai Huang wrote:
It's possible domain has already been in log-dirty mode when creating vcpu, in
which case we should enable PML for this vcpu if PML has been enabled for the
domain.
Signed-off-by: Kai Huang
---
xen/arc
On Mon, Mar 30, 2015 at 5:36 PM, Andrew Cooper
wrote:
> On 30/03/15 07:11, Kai Huang wrote:
>>
>>
>> On 03/28/2015 04:38 AM, Andrew Cooper wrote:
>>> On 27/03/15 02:35, Kai Huang wrote:
>>>> PML requires A/D bit support so enable it for furth
On Mon, Mar 30, 2015 at 5:54 PM, Andrew Cooper
wrote:
> On 30/03/15 07:43, Kai Huang wrote:
>>
>>
>> On 03/28/2015 05:09 AM, Andrew Cooper wrote:
>>> On 27/03/15 02:35, Kai Huang wrote:
>>>
>>>> +}
>>>> +
>>>> +int vmx_vcp
On 03/28/2015 04:42 AM, Andrew Cooper wrote:
On 27/03/15 02:35, Kai Huang wrote:
A top level EPT parameter "ept=" and a sub boolean "pml_enable" are
added to control PML. Other booleans can be further added for any other EPT
related features.
Signed-off-by: Kai Huang
Pl
On 03/28/2015 04:38 AM, Andrew Cooper wrote:
On 27/03/15 02:35, Kai Huang wrote:
PML requires A/D bit support so enable it for further use.
Signed-off-by: Kai Huang
---
xen/arch/x86/hvm/vmx/vmcs.c| 1 +
xen/arch/x86/mm/p2m-ept.c | 8 +++-
xen/include/asm-x86/hvm/vmx
On Thu, Apr 2, 2015 at 5:58 PM, Andrew Cooper wrote:
> On 02/04/15 06:46, Kai Huang wrote:
>>
>>
>> On 03/28/2015 04:42 AM, Andrew Cooper wrote:
>>> On 27/03/15 02:35, Kai Huang wrote:
>>>> A top level EPT parameter "ept=" and a sub boolean
&g
Hi all,
PML (Page Modification Logging) is a new feature on Intel's Boardwell server
platfrom targeted to reduce overhead of dirty logging mechanism. Below is the
design for Xen. Would you help to review and give comments?
Background
==
Currently, dirty logging is done via write prote
On 02/11/2015 09:13 PM, Jan Beulich wrote:
On 11.02.15 at 12:52, wrote:
On 11/02/15 08:28, Kai Huang wrote:
With PML, we don't have to use write protection but just clear D-bit
of EPT entry of guest memory to do dirty logging, with an additional
PML buffer full VMEXIT for 512 dirty
On 02/11/2015 07:52 PM, Andrew Cooper wrote:
On 11/02/15 08:28, Kai Huang wrote:
Hi all,
PML (Page Modification Logging) is a new feature on Intel's Boardwell
server platfrom targeted to reduce overhead of dirty logging
mechanism. Below is the design for Xen. Would you help to review and
On 02/11/2015 09:06 PM, Jan Beulich wrote:
On 11.02.15 at 09:28, wrote:
- PML enable/disable for particular Domain
PML needs to be enabled (allocate PML buffer, initialize PML index, PML base
address, turn PML on VMCS, etc) for all vcpus of the domain, as PML buffer
and PML index are per-vcpu
On 02/12/2015 10:49 AM, Kai Huang wrote:
On 02/11/2015 09:06 PM, Jan Beulich wrote:
On 11.02.15 at 09:28, wrote:
- PML enable/disable for particular Domain
PML needs to be enabled (allocate PML buffer, initialize PML index,
PML base
address, turn PML on VMCS, etc) for all vcpus of the
On 02/12/2015 02:25 PM, Tian, Kevin wrote:
From: Kai Huang [mailto:kai.hu...@linux.intel.com]
Sent: Thursday, February 12, 2015 10:35 AM
On 02/11/2015 09:13 PM, Jan Beulich wrote:
On 11.02.15 at 12:52, wrote:
On 11/02/15 08:28, Kai Huang wrote:
With PML, we don't have to use
On 02/12/2015 02:54 PM, Tian, Kevin wrote:
From: Kai Huang [mailto:kai.hu...@linux.intel.com]
Sent: Thursday, February 12, 2015 10:39 AM
PML needs to be enabled (allocate PML buffer, initialize PML index,
PML base address, turn PML on VMCS, etc) for all vcpus of the domain,
as PML buffer and
On 02/12/2015 03:02 PM, Tian, Kevin wrote:
From: Kai Huang [mailto:kai.hu...@linux.intel.com]
Sent: Thursday, February 12, 2015 10:50 AM
- PML buffer flush
There are two places we need to flush PML buffer. The first place is PML
buffer full VMEXIT handler (apparently), and the second place
On 02/12/2015 03:09 PM, Tian, Kevin wrote:
From: Kai Huang [mailto:kai.hu...@linux.intel.com]
Sent: Thursday, February 12, 2015 2:57 PM
On 02/12/2015 02:54 PM, Tian, Kevin wrote:
From: Kai Huang [mailto:kai.hu...@linux.intel.com]
Sent: Thursday, February 12, 2015 10:39 AM
PML needs to be
On 02/12/2015 03:08 PM, Tian, Kevin wrote:
From: Kai Huang [mailto:kai.hu...@linux.intel.com]
Sent: Thursday, February 12, 2015 2:46 PM
On 02/12/2015 02:25 PM, Tian, Kevin wrote:
From: Kai Huang [mailto:kai.hu...@linux.intel.com]
Sent: Thursday, February 12, 2015 10:35 AM
On 02/11/2015 09:13
On 02/12/2015 10:10 PM, Andrew Cooper wrote:
On 12/02/15 06:54, Tian, Kevin wrote:
which presumably
means that the PML buffer flush needs to be aware of which gfns are
mapped by superpages to be able to correctly set a block of bits in the
logdirty bitmap.
Unfortunately PML itself can't tell
On 02/12/2015 08:42 PM, Tim Deegan wrote:
At 07:08 + on 12 Feb (1423721283), Tian, Kevin wrote:
for general log dirty, ept_invalidate_emt is required because there is
access permission change (dirtied page becomes rw after 1st fault,
so need to change them back to ro again for the new dirty
On 02/12/2015 08:34 PM, Tim Deegan wrote:
Hi,
Thanks for posting this design!
At 16:28 +0800 on 11 Feb (1423668493), Kai Huang wrote:
Design
==
- PML feature is used globally
A new Xen boot parameter, say 'opt_enable_pml', will be introduced to control
PML feature detectio
On Fri, Feb 13, 2015 at 6:57 PM, Andrew Cooper
wrote:
> On 13/02/15 02:11, Kai Huang wrote:
>
>
> On 02/12/2015 10:10 PM, Andrew Cooper wrote:
>
> On 12/02/15 06:54, Tian, Kevin wrote:
>
> which presumably
> means that the PML buffer flush needs to be aware of
On Fri, Feb 13, 2015 at 11:28 PM, Andrew Cooper
wrote:
> On 13/02/15 14:32, Kai Huang wrote:
>> On Fri, Feb 13, 2015 at 6:57 PM, Andrew Cooper
>> wrote:
>>> On 13/02/15 02:11, Kai Huang wrote:
>>>
>>>
>>> On 02/12/2015 10:10 PM, Andrew Cooper
On Fri, Feb 13, 2015 at 11:52 PM, Kai Huang wrote:
> On Fri, Feb 13, 2015 at 11:28 PM, Andrew Cooper
> wrote:
>> On 13/02/15 14:32, Kai Huang wrote:
>>> On Fri, Feb 13, 2015 at 6:57 PM, Andrew Cooper
>>> wrote:
>>>> On 13/02/15 02:11, Kai Huang wr
On Fri, Feb 13, 2015 at 10:50 AM, Kai Huang wrote:
>
> On 02/12/2015 08:34 PM, Tim Deegan wrote:
>>
>> Hi,
>>
>> Thanks for posting this design!
>>
>> At 16:28 +0800 on 11 Feb (1423668493), Kai Huang wrote:
>>>
>>> Design
>>>
On Mon, Feb 16, 2015 at 7:44 PM, Andrew Cooper
wrote:
> On 14/02/15 03:01, Kai Huang wrote:
>>>> This will only function correctly if superpage shattering is used.
>>>>
>>>> As soon as a superpage D bit transitions from 0 to 1, the gfn is logged
>>>
On 02/17/2015 06:23 PM, Jan Beulich wrote:
On 12.02.15 at 03:49, wrote:
On 02/11/2015 09:06 PM, Jan Beulich wrote:
On 11.02.15 at 09:28, wrote:
- PML buffer flush
There are two places we need to flush PML buffer. The first place is PML
buffer full VMEXIT handler (apparently), and the secon
On 09/24/2015 05:10 PM, Tim Deegan wrote:
At 01:02 -0600 on 24 Sep (1443056566), Jan Beulich wrote:
On 23.09.15 at 17:46, wrote:
At 16:18 +0100 on 23 Sep (1443025126), Wei Liu wrote:
With the discussion still not finalised I'm a bit worried that this
issue will block the release.
I think w
setting the flag should be
> sufficient - the domain is required to be paused for PML enabling
> anyway, i.e. hardware will pick up the new setting the next time
> each vCPU of the guest gets scheduled.
>
> Signed-off-by: Jan Beulich
> Cc: Kai Huang
> ---
> VT-x maintainers, K
On Mon, Sep 28, 2015 at 10:09 PM, Jan Beulich wrote:
On 28.09.15 at 14:39, wrote:
>> --- a/xen/arch/x86/mm/p2m-ept.c
>> +++ b/xen/arch/x86/mm/p2m-ept.c
>> @@ -34,6 +34,8 @@
>>
>> #include "mm-locks.h"
>>
>> +static bool_t __read_mostly cpu_has_ept_ad;
>
> This should be
> #define cpu_has_ep
gt; anyway, i.e. hardware will pick up the new setting the next time
>>> each vCPU of the guest gets scheduled.
>>>
>>> Signed-off-by: Jan Beulich
>>> Cc: Kai Huang
>>> ---
>>> VT-x maintainers, Kai: Me lacking the hardware to test this, may
Hi,
I built and installed Xen from latest upstream Xen source code, but XL
always failed to work. Do you know what's going on here? My
environment is Lubuntu 14.04. Thanks in advance.
I always got "Permission denied" error.
root@kai-haswell:~# xl list
libxl: error: libxl.c:561:libxl_list_domain:
On 10/02/2015 05:36 PM, Wei Liu wrote:
On Wed, Sep 30, 2015 at 01:25:49PM +0100, Wei Liu wrote:
On Wed, Sep 30, 2015 at 05:36:22AM -0600, Jan Beulich wrote:
Since commit 191b3f3344ee ("p2m/ept: enable PML in p2m-ept for
log-dirty"), the A and D bits of EPT paging entries are set
unconditional
Hi Jan,
Our QA tested this patch but this patch broke PML. Neither GUI display
(video ram tracking also uses PML) nor live migration works. I'll
investigate what's wrong and get back to you.
Thanks,
-Kai
On 09/30/2015 08:45 PM, Kai Huang wrote:
On Wed, Sep 30, 2015 at 5:54 PM, J
efer the latter, please provide comments.
Thanks,
-Kai
On 10/14/2015 09:19 AM, Kai Huang wrote:
Hi Jan,
Our QA tested this patch but this patch broke PML. Neither GUI display
(video ram tracking also uses PML) nor live migration works. I'll
investigate what's wrong and get back to y
On 10/14/2015 05:26 PM, Jan Beulich wrote:
On 14.10.15 at 11:08, wrote:
After some thinking, just set/clear p2m->ept.ept_ad is not enough -- we
also need to __vmwrite it to VMCS's EPTP, and then call ept_sync_domain.
Ah, yes, this makes sense of course.
I have verified attached patch can w
On 10/15/2015 03:11 PM, Jan Beulich wrote:
On 15.10.15 at 08:42, wrote:
Thanks for your comments Jan. Actually I am not happy with combining
with EPT A/D bit update with PML enabling to single function. After
thinking again, how about adding a separate vmx function (ex,
vmx_domain_update_eptp
On 10/15/2015 03:35 PM, Kai Huang wrote:
On 10/15/2015 03:11 PM, Jan Beulich wrote:
On 15.10.15 at 08:42, wrote:
Thanks for your comments Jan. Actually I am not happy with combining
with EPT A/D bit update with PML enabling to single function. After
thinking again, how about adding a
anity live migration and GUI display were tested on Broadwell Machine.
Signed-off-by: Kai Huang
Signed-off-by: Jan Beulich
---
xen/arch/x86/hvm/vmx/vmcs.c| 24
xen/arch/x86/mm/p2m-ept.c | 24
xen/include/asm-x86/hvm/vmx/vmcs.h | 2 +
extra feature for
every
domain when we're not meaning to use it (yet).
Sanity live migration and GUI display were tested on Broadwell Machine.
Signed-off-by: Kai Huang
Signed-off-by: Jan Beulich
There's so little in this patch that came from me that I don't think this is
warranted; but
ded ASSERT of domain having been paused to ept_flush_pml_buffers to make
it consistent with ept_enable{disable}_pml.
Sanity live migration and GUI display were tested on Broadwell Machine.
Signed-off-by: Kai Huang
Suggested-by: Jan Beulich
---
xen/arch/x86/hvm/vmx/vmcs.c
Patch 1 is the v2 of defering enabling of EPT A/D bit until PML get enabled,
with comments from Jan in v1 addressed. Patch 2 is coding style fix of
for_each_vcpu to existing PML functions according to Jan.
Kai Huang (2):
x86/ept: defer enabling of EPT A/D bit until PML get enabled.
x86/vmx
According to Jan's comments, also fix the coding style of for_each_vcpu in
existing PML functions.
Signed-off-by: Kai Huang
---
xen/arch/x86/hvm/vmx/vmcs.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/xen/arch/x86/hvm/vmx/vmcs.c b/xen/arch/x86/hvm/vmx/vmcs.c
Hi Kevin,
Would you comment on the two patches?
Thanks,
-Kai
On 10/20/2015 10:34 AM, Kai Huang wrote:
Patch 1 is the v2 of defering enabling of EPT A/D bit until PML get enabled,
with comments from Jan in v1 addressed. Patch 2 is coding style fix of
for_each_vcpu to existing PML functions
Hi Jan, Tim, other maintainers,
Do you have comments? Or should I send out the v2 addressing Andrew's
comments, as it's been more than a week since this patch series were
sent out?
Thanks,
-Kai
On 03/30/2015 01:50 PM, Kai Huang wrote:
On 03/28/2015 05:26 AM, Andrew Cooper wro
On 04/07/2015 05:24 PM, Tim Deegan wrote:
Hi,
At 16:30 +0800 on 07 Apr (1428424218), Kai Huang wrote:
Hi Jan, Tim, other maintainers,
Do you have comments? Or should I send out the v2 addressing Andrew's
comments, as it's been more than a week since this patch series were
sent
The patch adds PML definition and feature detection. Note PML won't be detected
if PML is disabled from boot parameter. PML is also disabled in construct_vmcs,
as it will only be enabled when domain is switched to log dirty mode.
Signed-off-by: Kai Huang
---
xen/arch/x86/hvm/vmx/v
72811 80257 80139
72486 80413 81127
avg 72959 80718 81151
100%110.63% 111.22%
Kai Huang (11):
vmx: add new boot parameter to control PML enabling
doc: add description for new PML boot paramet
;t have to be initialized to zero explicitly as both
vcpu and domain structure are zero-ed when they are created.
Signed-off-by: Kai Huang
---
xen/include/asm-x86/hvm/vmx/vmcs.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/xen/include/asm-x86/hvm/vmx/vmcs.h
b/xen/include/asm-x86/hvm
We need to flush PML buffer when it's full.
Signed-off-by: Kai Huang
---
xen/arch/x86/hvm/vmx/vmx.c | 4
1 file changed, 4 insertions(+)
diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c
index 2ac1492..279e745 100644
--- a/xen/arch/x86/hvm/vmx/vmx.c
+++ b/xen/arc
refore we introduce
paging_mark_gfn_dirty which is bulk of paging_mark_dirty but takes guest pfn as
parameter, and in flushing PML buffer we call paging_mark_gfn_dirty directly.
Original paging_mark_dirty then simply is a wrapper of paging_mark_gfn_dirty.
Signed-off-by: Kai Huang
---
xen/arch/
This patch adds doc description for new boot parameter 'ept=pml'.
Signed-off-by: Kai Huang
---
docs/misc/xen-command-line.markdown | 14 ++
1 file changed, 14 insertions(+)
diff --git a/docs/misc/xen-command-line.markdown
b/docs/misc/xen-command-line.markdown
ind
A top level EPT parameter "ept=" and a sub boolean "opt_pml_enabled"
are added to control PML. Other booleans can be further added for any other EPT
related features.
Signed-off-by: Kai Huang
---
xen/arch/x86/hvm/vmx/vmcs.c | 31 +++
1 file ch
It's possible domain still remains in log-dirty mode when it is about to be
destroyed, in which case we should manually disable PML for it.
Signed-off-by: Kai Huang
---
xen/arch/x86/hvm/vmx/vmx.c | 8
1 file changed, 8 insertions(+)
diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen
It's possible domain has already been in log-dirty mode when creating vcpu, in
which case we should enable PML for this vcpu if PML has been enabled for the
domain.
Signed-off-by: Kai Huang
---
xen/arch/x86/hvm/vmx/vmx.c | 23 +++
1 file changed, 23 insertions(+)
diff
nctions to enable/disable PML and flush PML
buffers. The new functions are named to be generic to cover potential futher
PML-like features for other platforms.
Signed-off-by: Kai Huang
---
xen/arch/x86/mm/hap/hap.c | 29 +
xen/arch/x86/mm/p2m.
This patch adds help functions to enable/disable PML, and flush PML buffer for
single vcpu and particular domain for further use.
Signed-off-by: Kai Huang
---
xen/arch/x86/hvm/vmx/vmcs.c| 178 +
xen/include/asm-x86/hvm/vmx/vmcs.h | 9 ++
2 files
in order to log that GFN. For superpages, we still need to set it
to read-only as we need to split superpage to 4K pages in EPT violation.
Signed-off-by: Kai Huang
---
xen/arch/x86/mm/p2m-ept.c | 79 ++
xen/include/asm-x86/hvm/vmx/vmcs.h | 3 +-
xen
On Wed, Apr 15, 2015 at 8:20 PM, Jan Beulich wrote:
On 15.04.15 at 09:03, wrote:
>> +static void __init parse_ept_param(char *s)
>> +{
>> +char *ss;
>> +int val;
>
> bool_t, and would better move ...
>
>> +
>> +do {
>> +val = !!strncmp(s, "no-", 3);
>
> ... here (making t
On 04/15/2015 06:15 PM, Andrew Cooper wrote:
On 15/04/15 08:03, Kai Huang wrote:
This patch adds doc description for new boot parameter 'ept=pml'.
Signed-off-by: Kai Huang
Personally, I would fold this patch into the previous so the
documentation is in the same patch as intr
Thanks Tim!
I'll send out the v3 addressing minor comments from Andrew and Jan
regarding to patch 1 & 2.
Thanks,
-Kai
On Thu, Apr 16, 2015 at 10:41 PM, Tim Deegan wrote:
> At 15:03 +0800 on 15 Apr (1429110222), Kai Huang wrote:
>> This v2 patch series was rebased on la
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