flight 113041 linux-linus real [real]
http://logs.test-lab.xenproject.org/osstest/logs/113041/
Regressions :-(
Tests which did not succeed and are blocking,
including tests which could not be run:
test-amd64-i386-xl-qemut-win7-amd64 16 guest-localmigrate/x10 fail REGR. vs.
113031
test-amd64-i3
Oleksandr Andrushchenko wrote:
>>> We understand that emulated interrupt on the frontend side is completely not
>>> acceptable
Allow me to expand on that: Proper synchronization requires that the
exact position is communicated, not estimated. Just because the nominal
rate of the stream is known
Hello,
Sorry for such a long delay. I'm still interested in having this patch
merged.
I've tried to make the patch more generic and move it to xenbus as
discussed during the Xen summit, but I'm not sure how or if it's
possible. Would doing something in xenbus_otherend_changed() make sense?
But do
05/09/2017 05:41, Tan, Jianfeng:
> From: Richardson, Bruce
> >
> > Reading the contributors guide section on ABI, specifically
> > http://dpdk.org/doc/guides/contributing/versioning.html#deprecating-an-
> > entire-abi-version
> > it seems like we should collapse down the versions to a single one
>
On 05/09/2017 07:57, Jan Beulich wrote:
Andrew Cooper 09/04/17 7:35 PM >>>
>> Grp7 is abnormally complicated to decode, even by x86's standards, with
>> {s,l}msw being the problematic cases.
>>
>> Previously, any value which fell through the first switch statement (looking
>> for instructions
> -Original Message-
> From: Thomas Monjalon [mailto:tho...@monjalon.net]
> Sent: Tuesday, September 5, 2017 3:31 PM
> To: Tan, Jianfeng
> Cc: Richardson, Bruce; d...@dpdk.org; xen-de...@lists.xenproject.org;
> Mcnamara, John; joao.m.mart...@oracle.com;
> jerin.ja...@caviumnetworks.com; s
05/09/2017 10:07, Tan, Jianfeng:
> From: Thomas Monjalon [mailto:tho...@monjalon.net]
> > 05/09/2017 05:41, Tan, Jianfeng:
> > > From: Richardson, Bruce
> > > >
> > > > Reading the contributors guide section on ABI, specifically
> > > > http://dpdk.org/doc/guides/contributing/versioning.html#deprec
> -Original Message-
> From: Roger Pau Monne
> Sent: 04 September 2017 11:48
> To: Paul Durrant
> Cc: xen-de...@lists.xenproject.org; Wei Liu ; Ian
> Jackson
> Subject: Re: [Xen-devel] [PATCH v3 04/12] tools/libxenforeignmemory:
> reduce xenforeignmemory_restrict code footprint
>
> On Th
Grp7 is abnormally complicated to decode, even by x86's standards, with
{s,l}msw being the problematic cases.
Previously, any value which fell through the first switch statement (looking
for instructions with entirely implicit operands) would be interpreted by the
second switch statement (handling
In this commit, we extend the capabilities of the monitor to allow
tracing of single-step events on ARM.
Signed-off-by: Sergej Proskurin
---
Cc: Razvan Cojocaru
Cc: Tamas K Lengyel
Cc: Stefano Stabellini
Cc: Julien Grall
---
xen/arch/arm/monitor.c| 23 +++
xen/inc
This commit adds the domctl that is required to enable single-stepping
on ARM.
Signed-off-by: Sergej Proskurin
---
Cc: Stefano Stabellini
Cc: Julien Grall
---
xen/arch/arm/domctl.c| 35 +++
xen/include/asm-arm/domain.h | 2 ++
2 files changed, 37 insert
This commit concludes the single-stepping functionality on ARM by adding
trapping on and setting up single-stepping events of the architecture.
Signed-off-by: Sergej Proskurin
---
Cc: Stefano Stabellini
Cc: Julien Grall
---
xen/arch/arm/arm64/entry.S | 2 ++
xen/arch/arm/traps.c
In this commit we move the declaration of the function
vm_event_toggle_singlestep from to and
implement the associated functionality on ARM.
Signed-off-by: Sergej Proskurin
---
Cc: Razvan Cojocaru
Cc: Tamas K Lengyel
Cc: Stefano Stabellini
Cc: Julien Grall
Cc: Jan Beulich
Cc: Andrew Cooper
Hi all,
This patch series introduces support for single-stepping of guest VMs on
ARMv8. For detailed information about the single-stepping mechanism on
ARMv8, we refer the reader to ARM DDI 0487B.a Section D2.12 (Software
Step exceptions).
Our current implementation supports a rudimentary single-
The returned value represents now units of bytes instead of longs.
Fixes commit 11d0044a16 ("tools/libxc: Modify bitmap operations to take void
pointers")
Signed-off-by: Olaf Hering
---
tools/libxc/xc_bitops.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tools/libxc/xc_b
> -Original Message-
> From: Roger Pau Monne
> Sent: 04 September 2017 14:41
> To: Paul Durrant
> Cc: xen-de...@lists.xenproject.org; Andrew Cooper
> ; Jan Beulich
> Subject: Re: [Xen-devel] [PATCH v3 08/12] x86/hvm/ioreq: maintain an array
> of ioreq servers rather than a list
>
> On Th
CC Lars as well.
On Mon, Sep 04, 2017 at 02:44:43PM +0100, Wei Liu wrote:
> Make clear that blktap2 is orphaned to set expectation straight.
>
> Cc: Andrew Cooper
> Cc: George Dunlap
> Cc: Ian Jackson
> Cc: Jan Beulich
> Cc: Konrad Rzeszutek Wilk
> Cc: Stefano Stabellini
> Cc: Tim Deegan
>
flight 72062 distros-debian-snapshot real [real]
http://osstest.xs.citrite.net/~osstest/testlogs/logs/72062/
Regressions :-(
Tests which did not succeed and are blocking,
including tests which could not be run:
test-amd64-i386-i386-weekly-netinst-pygrub 4 host-install(4) broken REGR. vs.
72035
On Mon, Sep 04, 2017 at 09:58:07PM +0530, Bhupinder Thakur wrote:
> Hi Jan,
>
>
> On 28 August 2017 at 14:41, Jan Beulich wrote:
> On 28.08.17 at 10:56, wrote:
> >> --- a/config/arm32.mk
> >> +++ b/config/arm32.mk
> >> @@ -1,5 +1,6 @@
> >> CONFIG_ARM := y
> >> CONFIG_ARM_32 := y
> >> +CO
On 09/05/2017 11:57 AM, Sergej Proskurin wrote:
> In this commit, we extend the capabilities of the monitor to allow
> tracing of single-step events on ARM.
>
> Signed-off-by: Sergej Proskurin
Acked-by: Razvan Cojocaru
___
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Xen-
On 09/05/2017 11:57 AM, Sergej Proskurin wrote:
> In this commit we move the declaration of the function
> vm_event_toggle_singlestep from to and
> implement the associated functionality on ARM.
>
> Signed-off-by: Sergej Proskurin
Acked-by: Razvan Cojocaru
Thanks,
Razvan
__
>>> On 05.09.17 at 09:34, wrote:
> On 05/09/2017 07:57, Jan Beulich wrote:
> Andrew Cooper 09/04/17 7:35 PM >>>
>>> Grp7 is abnormally complicated to decode, even by x86's standards, with
>>> {s,l}msw being the problematic cases.
>>>
>>> Previously, any value which fell through the first swit
flight 113042 linux-3.18 real [real]
http://logs.test-lab.xenproject.org/osstest/logs/113042/
Failures and problems with tests :-(
Tests which did not succeed and are blocking,
including tests which could not be run:
build-arm64-pvops 3 capture-logs broken REGR. vs. 112102
This patch implements get value domctl interface for MBA.
Signed-off-by: Yi Sun
Reviewed-by: Roger Pau Monné
---
v3:
- change 'PSR_VAL_TYPE_MBA' to 'PSR_TYPE_MBA_THRTL'.
(suggested by Roger Pau Monné)
---
xen/arch/x86/domctl.c | 7 +++
xen/include/public/domctl.h | 1 +
2 fi
Hi, all,
We plan to bring a new PSR (Platform Shared Resource) feature called
Intel Memory Bandwidth Allocation (MBA) to Xen.
Besides the MBA enabling, we change some interfaces to make them more
general but not only for CAT.
Any comments are welcome!
You can find this series at:
https://github
This patch creates MBA feature document in doc/features/. It describes
key points to implement MBA which is described in details in Intel SDM
"Introduction to Memory Bandwidth Allocation".
Signed-off-by: Yi Sun
---
v3:
- remove 'closed-loop' related description.
(suggested by Roger Pau
This patch implements get HW info flow for MBA including its callback
function and sysctl interface.
Signed-off-by: Yi Sun
---
v3:
- replace 'PSR_VAL_TYPE_MBA' to 'PSR_TYPE_MBA_THRTL'.
(suggested by Roger Pau Monné)
v2:
- use 'XEN_SYSCTL_PSR_MBA_LINEAR' to set MBA feature HW info.
This patch renames PSR sysctl/domctl interfaces and related xsm policy to
make them be general for all resource allocation features but not only
for CAT. Then, we can resuse the interfaces for all allocation features.
Basically, it changes 'psr_cat/PSR_CAT' to 'psr_alloc/PSR_ALLOC' and remove
'op/
This patch implements main data structures of MBA.
Like CAT features, MBA HW info has cos_max which means the max thrtl
register number, and thrtl_max which means the max throttle value
(delay value). It also has a flag to represent if the throttle
value is linear or not.
One thrtl register of MB
This patch renames 'cbm_type' to 'psr_type' to make it be general.
Then, we can reuse this for all psr allocation features.
Signed-off-by: Yi Sun
Reviewed-by: Wei Liu
---
v3:
- replace 'psr_val_type' to 'psr_type' and remove '_VAL' from the enum
items.
(suggested by Roger Pau Mon
This patch creates general interfaces in libxl to support all psr
allocation features.
Add 'LIBXL_HAVE_PSR_GENERIC' to indicate interface change.
Please note, the functionality cannot work until later patches
are applied.
Signed-off-by: Yi Sun
---
v3:
- change 'LIBXL_HAVE_PSR_MBA' to 'LIBXL
This patch implements set value flow for MBA including its callback
function and domctl interface.
It also changes the memebers in 'cos_write_info' to transfer the
feature array, feature properties array and value array. Then, we
can write all features values on the cos id into MSRs.
Because mult
This patch implements the new libxl get hw info interface,
'libxl_psr_get_hw_info', which is suitable to all psr allocation
features. It also implements corresponding list free function,
'libxl_psr_hw_info_list_free' and make 'libxl_psr_cat_get_info' to call
'libxl_psr_get_hw_info' to avoid redunda
This patch implements generic get value interfaces in libxc and libxl.
It also refactors the get value flow in xl to make it be suitable for all
allocation features. Based on that, a new MBA get value command is added in xl.
Signed-off-by: Yi Sun
Acked-by: Wei Liu
---
v3:
- replace 'libxl_ps
This patch adds MBA description in related documents.
Signed-off-by: Yi Sun
Acked-by: Wei Liu
---
v2:
- state the value type shown by 'psr-mba-show'. For linear mode,
it shows decimal value. For non-linear mode, it shows hexadecimal
value.
(suggested by Chao Peng)
---
docs
This patch implements a new xl get HW info interface. A new argument
is added for psr-hwinfo command to get and show MBA HW info.
Signed-off-by: Yi Sun
---
v3:
- change the format string of printf in 'psr_mba_hwinfo'.
(suggested by Roger Pau Monné)
- add 'const' for 'opts[]' in 'mai
This patch implements a new libxc get hw info interface and corresponding
data structures. It also changes libxl_psr.c to call this new interface.
Signed-off-by: Yi Sun
---
v3:
- rename 'psr_cat/PSR_CAT' to 'psr_alloc/PSR_ALLOC' and remove 'op/OP'
from name.
(suggested by Roger Pa
This patch implements new generic set value interfaces in libxc and libxl.
These interfaces are suitable for all allocation features. It also adds a
new MBA set value command in xl.
Signed-off-by: Yi Sun
---
v3:
- add 'const' for 'opts[]' in 'main_psr_mba_set'.
(suggested by Roger Pau M
This patch renames 'xc_psr_cat_type' to 'xc_psr_type' so that
the structure name is common for all allocation features.
Signed-off-by: Yi Sun
Acked-by: Wei Liu
Reviewed-by: Chao Peng
---
v3:
- change 'xc_psr_val_type' to 'xc_psr_type'.
(suggested by Roger Pau Monné)
---
tools/libxc/i
On 05/09/2017 10:43, Jan Beulich wrote:
On 05.09.17 at 09:34, wrote:
>> On 05/09/2017 07:57, Jan Beulich wrote:
>> Andrew Cooper 09/04/17 7:35 PM >>>
Grp7 is abnormally complicated to decode, even by x86's standards, with
{s,l}msw being the problematic cases.
Previous
>>> On 05.09.17 at 11:53, wrote:
> On 05/09/2017 10:43, Jan Beulich wrote:
> On 05.09.17 at 09:34, wrote:
>>> On 05/09/2017 07:57, Jan Beulich wrote:
>>> Andrew Cooper 09/04/17 7:35 PM >>>
> Grp7 is abnormally complicated to decode, even by x86's standards, with
> {s,l}msw being
>>> On 05.09.17 at 10:41, wrote:
> +case GRP7_MEM(0): /* sgdt */
> +case GRP7_MEM(1): /* sidt */
> generate_exception_if(ea.type != OP_MEM, EXC_UD);
As implied on the v2 thread - with these converted to ASSERT()
Reviewed-by: Jan Beulich
Jan
___
flight 113046 libvirt real [real]
http://logs.test-lab.xenproject.org/osstest/logs/113046/
Regressions :-(
Tests which did not succeed and are blocking,
including tests which could not be run:
build-armhf-libvirt 6 libvirt-buildfail REGR. vs. 113032
Tests which did not suc
This patch changes use of bool_t to bool in the ioreq server code. It also
fixes an incorrect indentation in a continuation line.
This patch is purely cosmetic. No semantic or functional change.
Signed-off-by: Paul Durrant
Reviewed-by: Roger Pau Monné
---
Cc: Jan Beulich
Cc: Andrew Cooper
---
A previous patch added support for priv-mapping guest resources directly
(rather than having to foreign-map, which requires P2M modification for
HVM guests).
This patch makes use of the new API to seed the guest grant table unless
the underlying infrastructure (i.e. privcmd) doesn't support it, in
A previous patch introduced a new HYPERVISOR_memory_op to acquire guest
resources for direct priv-mapping.
This patch adds new functionality into libxenforeignmemory to make use
of a new privcmd ioctl [1] that uses the new memory op to make such
resources available via mmap(2).
[1]
http://xenbit
This series introduces support for direct mapping of guest resources.
The resources are:
- Grant tables
- IOREQ server pages
NOTE: This series is based on a master re-base of Juergen Gross's patch "xen:
move
XENMAPSPACE_grant_table code into grant_table.c". For convenience the code is
also ava
By using a static inline stub in private.h for OS where this functionality
is not implemented, the various duplicate stubs in the OS-specific source
modules can be avoided.
Signed-off-by: Paul Durrant
Reviewed-by: Roger Pau Monné
---
Cc: Ian Jackson
Cc: Wei Liu
v4:
- Removed extraneous freeb
In the case where a PV domain is mapping guest resources then it needs make
the HYPERVISOR_mmu_update call using DOMID_SELF, rather than the guest
domid, so that the passed in gmfn values are correctly treated as mfns
rather than gfns present in the guest p2m.
This patch removes a check which curr
Since ioreq servers are only relevant to HVM guests and all the names in
question unequivocally refer to guest frame numbers, name them all .*gfn
to avoid any confusion.
This patch is purely cosmetic. No semantic or functional change.
Signed-off-by: Paul Durrant
Reviewed-by: Wei Liu
Reviewed-by
This patch re-works much of the ioreq server initialization and teardown
code:
- The hvm_map/unmap_ioreq_gfn() functions are expanded to call through
to hvm_alloc/free_ioreq_gfn() rather than expecting them to be called
separately by outer functions.
- Several functions now test the validity o
Certain memory resources associated with a guest are not necessarily
present in the guest P2M and so are not necessarily available to be
foreign-mapped by a tools domain unless they are inserted, which risks
shattering a super-page mapping.
This patch adds a new memory op to allow such a resource
A subsequent patch will remove the current implicit limitation on creation
of ioreq servers which is due to the allocation of gfns for the ioreq
structures and buffered ioreq ring.
It will therefore be necessary to introduce an explicit limit and, since
this limit should be small, it simplifies th
... XENMEM_resource_ioreq_server
This patch adds support for a new resource type that can be mapped using
the XENMEM_acquire_resource memory op.
If an emulator makes use of this resource type then, instead of mapping
gfns, the IOREQ server will allocate pages from the heap. These pages
will never
A subsequent patch will introduce a new scheme to allow an emulator to
map ioreq server pages directly from Xen rather than the guest P2M.
This patch lays the groundwork for that change by deferring mapping of
gfns until their values are requested by an emulator. To that end, the
pad field of the
This patch adjusts the ioreq server code to use type-safe gfn_t values
where possible. No functional change.
Signed-off-by: Paul Durrant
Reviewed-by: Roger Pau Monné
---
Cc: Andrew Cooper
Cc: Jan Beulich
---
xen/arch/x86/hvm/ioreq.c | 44
xen/i
On Tue, Jul 18, 2017 at 05:25:18PM +0300, Oleksandr Grytsov wrote:
> From: Oleksandr Grytsov
>
> Add libxl__device_add to simple write XenStore device conifg
> and libxl__device_add_async to update domain configuration
> and write XenStore device config asynchroniously.
> Almost all devices have
On Tue, Jul 18, 2017 at 05:25:19PM +0300, Oleksandr Grytsov wrote:
> From: Oleksandr Grytsov
>
> Add libxl__device_list and libxl__device_list_free
> functions to handle device list using the device
> framework.
>
> Signed-off-by: Oleksandr Grytsov
> ---
> tools/libxl/libxl_device.c | 66
>
On 10/07/17 11:39, Jan Beulich wrote:
> Real hardware wraps silently in most cases, so we should behave the
> same. Also split real and VM86 mode handling, as the latter really
> ought to have limit checks applied.
>
> Signed-off-by: Jan Beulich
The change looks ok, but this is a subtle adjustmen
flight 113045 ovmf real [real]
http://logs.test-lab.xenproject.org/osstest/logs/113045/
Perfect :-)
All tests in this flight passed as required
version targeted for testing:
ovmf 302860bfc467c72bdba91af021a44e20789601dc
baseline version:
ovmf c2ab95806bf0e5ae272f4
flight 113044 qemu-mainline real [real]
http://logs.test-lab.xenproject.org/osstest/logs/113044/
Regressions :-(
Tests which did not succeed and are blocking,
including tests which could not be run:
test-amd64-amd64-libvirt-qemuu-debianhvm-amd64-xsm 15 guest-stop fail REGR.
vs. 113036
Regressi
On 10/07/17 08:24, Jan Beulich wrote:
> Recent changes to the SDM (and XED) have made clear that older hardware
> raising #UD when the bit is set was really an erratum. Generalize the
> so far AMD-only override.
>
> Signed-off-by: Jan Beulich
Reviewed-by: Andrew Cooper
_
On Tue, Jul 18, 2017 at 05:25:20PM +0300, Oleksandr Grytsov wrote:
> From: Oleksandr Grytsov
>
> Signed-off-by: Oleksandr Grytsov
> ---
> tools/libxl/Makefile | 2 +-
> tools/libxl/libxl.h | 24 +++
> tools/libxl/libxl_create.c | 1 +
> tools/libx
On Tue, Jul 18, 2017 at 05:25:23PM +0300, Oleksandr Grytsov wrote:
> From: Oleksandr Grytsov
>
> Signed-off-by: Oleksandr Grytsov
This needs rebasing.
___
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On Tue, Jul 18, 2017 at 05:25:24PM +0300, Oleksandr Grytsov wrote:
> From: Oleksandr Grytsov
>
> Signed-off-by: Oleksandr Grytsov
Acked-by: Wei Liu
___
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Xen-devel@lists.xen.org
https://lists.xen.org/xen-devel
On Tue, Jul 18, 2017 at 05:25:25PM +0300, Oleksandr Grytsov wrote:
> From: Oleksandr Grytsov
>
> Signed-off-by: Oleksandr Grytsov
Acked-by: Wei Liu
___
Xen-devel mailing list
Xen-devel@lists.xen.org
https://lists.xen.org/xen-devel
Wei Liu writes ("Re: [PATCH v4 03/13] libxl: add vdispl device"):
> > +rc = snprintf(connector_path, 128, "%s/%d", path,
> > info->num_connectors);
Why not use GCSPRINTF ? These statically sized buffers etc. are an
invitation to bugs.
Ian.
___
Xe
On Tue, Jul 18, 2017 at 05:25:26PM +0300, Oleksandr Grytsov wrote:
> From: Oleksandr Grytsov
>
[...]
> /*
> * Insert a CD-ROM device. A device corresponding to disk must already
> diff --git a/tools/libxl/libxl_checkpoint_device.c
> b/tools/libxl/libxl_checkpoint_device.c
> index 01e74b5..7bd
On Tue, Jul 18, 2017 at 05:25:27PM +0300, Oleksandr Grytsov wrote:
> From: Oleksandr Grytsov
>
> Signed-off-by: Oleksandr Grytsov
> diff --git a/tools/libxl/libxl_nic.c b/tools/libxl/libxl_nic.c
> index dd07a6c..16a6c8c 100644
> --- a/tools/libxl/libxl_nic.c
> +++ b/tools/libxl/libxl_nic.c
> @@
On Tue, Sep 05, 2017 at 01:58:53PM +0100, Ian Jackson wrote:
> Wei Liu writes ("Re: [PATCH v4 03/13] libxl: add vdispl device"):
> > > +rc = snprintf(connector_path, 128, "%s/%d", path,
> > > info->num_connectors);
>
> Why not use GCSPRINTF ? These statically sized buffers etc. are an
> invi
On Tue, Jul 18, 2017 at 05:25:28PM +0300, Oleksandr Grytsov wrote:
> From: Oleksandr Grytsov
>
> Signed-off-by: Oleksandr Grytsov
Acked-by: Wei Liu
___
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On Tue, Jul 18, 2017 at 05:25:29PM +0300, Oleksandr Grytsov wrote:
> From: Oleksandr Grytsov
>
> Signed-off-by: Oleksandr Grytsov
Acked-by: Wei Liu
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On Tue, Jul 18, 2017 at 05:25:30PM +0300, Oleksandr Grytsov wrote:
> From: Oleksandr Grytsov
>
> Due to changes in device framework setdefault function
> should have same format. Otherwise calling devicetype
> set_default causes segfault.
>
> Signed-off-by: Oleksandr Grytsov
Shouldn't this pat
On 10/07/17 08:25, Jan Beulich wrote:
> While these are latent issues only for now, correct them right away:
> - EVEX.V' (called RX in our code) needs to uniformly be 1,
> - EXEX.R' (called R in our code) is uniformly being ignored.
>
> Signed-off-by: Jan Beulich
Those changes do match table 2-40
On Sat, Sep 02, 2017 at 01:56:35AM +0800, Zhongze Liu wrote:
> 2017-09-02 0:03 GMT+08:00 Wei Liu :
> > On Sun, Aug 27, 2017 at 04:36:12PM +0800, Zhongze Liu wrote:
> >> Add the parsing utils for the newly introduced libxl_static_sshm struct
> >> to the libxl/libxlu_* family. And add realated parsin
For XEN_SMEP and XEN_SMAP to not be cleared while bringing up APs we'd
need to clone the respective hack used for CPUID_FAULTING. Introduce an
inverse of setup_clear_cpu_cap() instead, but let clearing of features
overrule forced setting of them.
XEN_SMAP being wrong post-boot is a problem specifi
On Tue, Sep 05, 2017 at 11:03:38AM +0200, Olaf Hering wrote:
> The returned value represents now units of bytes instead of longs.
>
> Fixes commit 11d0044a16 ("tools/libxc: Modify bitmap operations to take void
> pointers")
>
> Signed-off-by: Olaf Hering
Acked-by: Wei Liu
___
Instead of special casing pv_lock_ops.vcpu_is_preempted when patching
use _paravirt_false() on bare metal.
Signed-off-by: Juergen Gross
---
arch/x86/kernel/paravirt-spinlocks.c | 14 +-
arch/x86/kernel/paravirt_patch_32.c | 10 --
arch/x86/kernel/paravirt_patch_64.c | 10 --
Add a _paravirt_false() default function returning always false which
can be used for cases where a boolean pvops replacement should just
say "no".
Signed-off-by: Juergen Gross
---
arch/x86/include/asm/paravirt_types.h | 2 ++
arch/x86/kernel/paravirt.c| 7 +++
arch/x86/kernel/pa
With virt_spin_lock() being a pvops function the bare metal case can be
optimized by patching the call away completely. In case a kernel running
as a guest it can decide whether to use paravitualized spinlocks, the
current fallback to the unfair test-and-set scheme, or to mimic the
bare metal behav
There are cases where a guest tries to switch spinlocks to bare metal
behavior (e.g. by setting "xen_nopvspin" boot parameter). Today this
has the downside of falling back to unfair test and set scheme for
qspinlocks due to virt_spin_lock() detecting the virtualized
environment.
Make virt_spin_loc
With the boot parameter "xen_nopvspin" specified a Xen guest should not
make use of paravirt spinlocks, but behave as if running on bare
metal. This is not true, however, as the qspinlock code will fall back
to a test-and-set scheme when it is detecting a hypervisor.
In order to avoid this set the
>>> On 05.09.17 at 14:26, wrote:
> On 10/07/17 11:39, Jan Beulich wrote:
>> Real hardware wraps silently in most cases, so we should behave the
>> same. Also split real and VM86 mode handling, as the latter really
>> ought to have limit checks applied.
>>
>> Signed-off-by: Jan Beulich
>
> The ch
>>> On 05.09.17 at 15:07, wrote:
> On 10/07/17 08:25, Jan Beulich wrote:
>> While these are latent issues only for now, correct them right away:
>> - EVEX.V' (called RX in our code) needs to uniformly be 1,
>> - EXEX.R' (called R in our code) is uniformly being ignored.
>>
>> Signed-off-by: Jan Be
On 10/07/17 08:24, Jan Beulich wrote:
> Going though the XED commits from the last couple of months made me
> notice that VPINSRD, other than VPEXTRD, does not clear VEX.W for non-
> 64-bit modes, leading to an insertion of stray 32-bits of zero in case
> the original instruction had the bit set.
>
>>> On 05.09.17 at 15:36, wrote:
On 05.09.17 at 15:07, wrote:
>> On 10/07/17 08:25, Jan Beulich wrote:
>> What about the opcode independent cases? We should check that the two
>> MBZ bits (currently an anonymous bitfield) are zero, and the MBS bit
>> (currently evex.evex) is set.
>
> Yes,
On Tue, Sep 05, 2017 at 03:24:43PM +0200, Juergen Gross wrote:
> diff --git a/arch/x86/include/asm/qspinlock.h
> b/arch/x86/include/asm/qspinlock.h
> index 48a706f641f2..fbd98896385c 100644
> --- a/arch/x86/include/asm/qspinlock.h
> +++ b/arch/x86/include/asm/qspinlock.h
> @@ -17,6 +17,25 @@ stati
While these are latent issues only for now, correct them right away:
- unnamed (in the SDM) EVEX bits need to be set/clear respectively
- EVEX.V' (called RX in our code) needs to uniformly be 1 in non-64-bit
modes,
- EXEX.R' (called R in our code) is uniformly being ignored in
non-64-bit modes.
On 05/09/17 15:55, Peter Zijlstra wrote:
> On Tue, Sep 05, 2017 at 03:24:43PM +0200, Juergen Gross wrote:
>> diff --git a/arch/x86/include/asm/qspinlock.h
>> b/arch/x86/include/asm/qspinlock.h
>> index 48a706f641f2..fbd98896385c 100644
>> --- a/arch/x86/include/asm/qspinlock.h
>> +++ b/arch/x86/in
On 09/05/2017 09:24 AM, Juergen Gross wrote:
> There are cases where a guest tries to switch spinlocks to bare metal
> behavior (e.g. by setting "xen_nopvspin" boot parameter). Today this
> has the downside of falling back to unfair test and set scheme for
> qspinlocks due to virt_spin_lock() detec
On 05/09/17 14:56, Jan Beulich wrote:
> While these are latent issues only for now, correct them right away:
> - unnamed (in the SDM) EVEX bits need to be set/clear respectively
> - EVEX.V' (called RX in our code) needs to uniformly be 1 in non-64-bit
> modes,
> - EXEX.R' (called R in our code) i
On Tue, Sep 05, 2017 at 10:02:57AM -0400, Waiman Long wrote:
> On 09/05/2017 09:24 AM, Juergen Gross wrote:
> > +static inline bool native_virt_spin_lock(struct qspinlock *lock)
> > +{
> > + if (!static_cpu_has(X86_FEATURE_HYPERVISOR))
> > + return false;
> > +
>
> I think you can tak
Instead, preserve PGC_need_scrub bit when setting PGC_state_inuse
state while still under the lock and clear those pages later.
Note that we still need to grub the lock when clearing PGC_need_scrub
bit since count_info might be updated during MCE handling in
mark_page_offline().
Signed-off-by: Bo
On 09/05/2017 09:24 AM, Juergen Gross wrote:
> There are cases where a guest tries to switch spinlocks to bare metal
> behavior (e.g. by setting "xen_nopvspin" boot parameter). Today this
> has the downside of falling back to unfair test and set scheme for
> qspinlocks due to virt_spin_lock() detec
On 05/09/17 16:10, Waiman Long wrote:
> On 09/05/2017 09:24 AM, Juergen Gross wrote:
>> There are cases where a guest tries to switch spinlocks to bare metal
>> behavior (e.g. by setting "xen_nopvspin" boot parameter). Today this
>> has the downside of falling back to unfair test and set scheme for
On 09/05/2017 10:08 AM, Peter Zijlstra wrote:
> On Tue, Sep 05, 2017 at 10:02:57AM -0400, Waiman Long wrote:
>> On 09/05/2017 09:24 AM, Juergen Gross wrote:
>>> +static inline bool native_virt_spin_lock(struct qspinlock *lock)
>>> +{
>>> + if (!static_cpu_has(X86_FEATURE_HYPERVISOR))
>>> +
On 09/05/2017 10:18 AM, Juergen Gross wrote:
> On 05/09/17 16:10, Waiman Long wrote:
>> On 09/05/2017 09:24 AM, Juergen Gross wrote:
>>> There are cases where a guest tries to switch spinlocks to bare metal
>>> behavior (e.g. by setting "xen_nopvspin" boot parameter). Today this
>>> has the downsid
>>> On 05.09.17 at 16:11, wrote:
> I couldn't convince myself that just marking the head as PGC_state_inuse
> under the lock is safe, mostly because of how MCE handler may write the
> state while the allocator is walking (lock-free) the buddy.
Good point.
> @@ -974,13 +972,39 @@ static struct pa
On 09/05/2017 10:24 AM, Waiman Long wrote:
> On 09/05/2017 10:18 AM, Juergen Gross wrote:
>> On 05/09/17 16:10, Waiman Long wrote:
>>> On 09/05/2017 09:24 AM, Juergen Gross wrote:
There are cases where a guest tries to switch spinlocks to bare metal
behavior (e.g. by setting "xen_nopvspin
This run is configured for baseline tests only.
flight 72063 ovmf real [real]
http://osstest.xs.citrite.net/~osstest/testlogs/logs/72063/
Perfect :-)
All tests in this flight passed as required
version targeted for testing:
ovmf 302860bfc467c72bdba91af021a44e20789601dc
baseline v
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