On Wed, Jun 28, 2017 at 06:55:58PM +0100, Wei Liu wrote:
> On Wed, Jun 28, 2017 at 12:10:20PM +0200, Marek Marczykowski-Górecki wrote:
> > This adds handling more cpuid bits by name. Mostly based on cpu_map.xml from
> > libvirt.
> >
> > Marek Marczykowski-Górecki (2):
> > libxl: add more cpuid f
On Thu, Jun 29, 2017 at 04:42:33PM +0100, Roger Pau Monné wrote:
>On Thu, Jun 29, 2017 at 11:21:53AM +0800, Chao Gao wrote:
>> The problem is for a VF of RC integrated PF (e.g. PF's BDF is 00:02.0),
>> we would wrongly use 00:00.0 to search VT-d unit.
>>
>> From SRIOV spec REV 1.0 section 3.7.3, i
The problem is for a VF of RC integrated PF (e.g. PF's BDF is 00:02.0),
we would wrongly use 00:00.0 to search VT-d unit.
From SRIOV spec REV 1.0 section 3.7.3, it says:
"ARI is not applicable to Root Complex integrated Endpoints; all other
SR-IOV Capable Devices (Devices that include at least one
flight 71 libvirt real [real]
http://logs.test-lab.xenproject.org/osstest/logs/71/
Regressions :-(
Tests which did not succeed and are blocking,
including tests which could not be run:
test-arm64-arm64-libvirt-qcow2 10 debian-di-install fail REGR. vs. 111061
Tests which did not suc
The "mmu-masters" is a property of ARM legacy SMMU dt-binding. This
property will be deprecated in favour of the generic IOMMU bindings.
In this case we have to add the generic IOMMU bindings support for
Xen platform devices.
---
This series has been tested on Seattle SoftIron server. The platform
The legacy IOMMU bindings place the SMMU MasterIDs in the SMMU device
tree node. In current code, we register the SMMU masters while probing
SMMU. It's better to keep registering legacy masters in the SMMU probing
progress. If we move registering legacy SMMU masters to add_device or
assign_device,
In previous code, while we are constructing Dom0, we will assign
all devices except passthrough devices to Dom0. In the later, when
we start the DomU, the assign_device will prepare SMMU resources
for the devices passthrough to DomU. This is ok when we kept the
add_device code in assign_device. But
It's a error message about XEN_DOMCTL_deassign_device, but the
print message is XEN_DOMCTL_assign_device.
Signed-off-by: Wei Chen
---
xen/drivers/passthrough/device_tree.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/xen/drivers/passthrough/device_tree.c
b/xen/drivers
The SMMU MasterIDs are placed at the master devices' DT node while
using the generic bindings. In this case, it's very hard for us to
register SMMU masters while probing SMMU as we had done for legacy
bindings. Because we have to go through whole device tree for all
SMMU devices to find their maste
In current code, we only have the iommu_add_device to add PCI device
to IOMMU. But for ARM SMMU, we don't have a separate helper to add
platform device with device tree to SMMU. This work was included in
the iommu_assign_dt_device. But sometimes, we just want to add device
to SMMU to do some prepar
This add_device callback function is taking care of adding a device
to SMMU and make sure it is fully prepare to be used by the SMMU
afterwards.
In previous code, we don't implement the add_device callback in
iommu_ops for ARM SMMU. We placed the work of add_device to
assign_device callback. The f
The device tree provides two types of IOMMU bindings, one is legacy
another is generic. The legacy bindings will be depercated in favour
of the generic bindings. But in the transitional period, we have to
support both of them.
The codes to handle these two types of bindings are very differnet,
so
Each PCI(e) device under a root complex is uniquely identified by its
Requester ID (AKA RID). A Requester ID is a triplet of a Bus number,
Device number, and Function number. IOMMUs may distinguish PCI devices
through sideband data derived from the Requester ID. While a given PCI
device can only ma
The legacy smmu binding will be deprecated in favour of the generic
"iommus" binding. So we need a new helper to parse generic iommu
bindings. When the system detects the SMMU is using generic iommu
binding, this helper will be called when this platform device is
assiged to a guest.
This patch is
The legacy IOMMU bindings will be deprecated in future. Instead, device
tree provide generic IOMMU bindings and PCI IOMMU bindings. Currently,
the PCI support hasn't been enabled on ARM Xen. So in this series, we
just add the support of parsing PCI IOMMU bindings.
Wei Chen (2):
xen: devicetree:
flight 77 qemu-mainline real [real]
http://logs.test-lab.xenproject.org/osstest/logs/77/
Failures :-/ but no regressions.
Tests which are failing intermittently (not blocking):
test-armhf-armhf-xl-xsm 4 host-install(4) broken in 42 pass in 77
test-armhf-armhf-xl-vhd 4
flight 98 ovmf real [real]
http://logs.test-lab.xenproject.org/osstest/logs/98/
Perfect :-)
All tests in this flight passed as required
version targeted for testing:
ovmf 0ad564ffe76f5a9286dd61a7b9e021e4b5cd0c0e
baseline version:
ovmf 03a5572bed61a5e0af83d
On 17-06-29 12:00:12, Jan Beulich wrote:
> >>> Yi Sun 06/14/17 3:25 AM >>>
> > +struct cos_write_info
> > +{
> > +unsigned int cos;
> > +struct feat_node *feature;
> > +uint32_t *val;
>
> const?
>
The member of feature, 'cos_reg_val', will be written in 'do_write_psr_msrs'.
So, I can
flight 91 linux-3.18 real [real]
http://logs.test-lab.xenproject.org/osstest/logs/91/
Regressions :-(
Tests which did not succeed and are blocking,
including tests which could not be run:
test-amd64-i386-qemut-rhel6hvm-amd 10 redhat-install fail REGR. vs. 110441
test-armhf-armhf-xl-
>>> Yi Sun 06/14/17 3:26 AM >>>
> @@ -253,6 +271,26 @@ static void cat_init_feature(const struct cpuid_leaf
> *regs,
>
> break;
>
> +case PSR_SOCKET_L3_CDP:
> +{
> +uint64_t val;
> +
> +/* Cut half of cos_max when CDP is enabled. */
> +feat->cos_max >>
>>> Yi Sun 06/14/17 3:26 AM >>>
> --- a/xen/arch/x86/psr.c
> +++ b/xen/arch/x86/psr.c
> @@ -217,7 +217,21 @@ static enum psr_feat_type psr_cbm_type_to_feat_type(enum
> cbm_type type)
> {
> case PSR_CBM_TYPE_L3:
> feat_type = PSR_SOCKET_L3_CAT;
> +
> +/*
> + * If
>>> Yi Sun 06/14/17 3:26 AM >>>
> This patch implements L3 CDP set value related callback function.
>
> With this patch, 'psr-cat-cbm-set' command can work for L3 CDP.
>
> Signed-off-by: Yi Sun
> ---
> v12:
> - add comment to explain how to deal with the case that user set new val
> f
>>> Yi Sun 06/30/17 7:46 AM >>>
>On 17-06-29 12:00:12, Jan Beulich wrote:
>> >>> Yi Sun 06/14/17 3:25 AM >>>
>> > +struct cos_write_info
>> > +{
>> > +unsigned int cos;
>> > +struct feat_node *feature;
>> > +uint32_t *val;
>>
>> const?
>>
>The member of feature, 'cos_reg_val', will
>>> Yi Sun 06/14/17 3:26 AM >>>
> @@ -279,10 +281,14 @@ static void cat_init_feature(const struct cpuid_leaf
> *regs,
> switch ( type )
> {
> case PSR_SOCKET_L3_CAT:
> +case PSR_SOCKET_L2_CAT:
> /* cos=0 is reserved as default cbm(all bits within cbm_len are 1).
> */
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