>>> On 14.02.17 at 18:35, wrote:
> At 06:37 -0700 on 13 Feb (1486967832), Jan Beulich wrote:
>> >>> On 13.02.17 at 14:19, wrote:
>> > -tss = mem_alloc(128, 128);
>> > -memset(tss, 0, 128);
>> > +tss = mem_alloc(TSS_SIZE, TSS_SIZE);
>>
>> tss = mem_alloc(TSS_SIZE, 128);
>>
>> is
Hi Stefano,
On 14 February 2017 at 03:14, Stefano Stabellini wrote:
> On Mon, 13 Feb 2017, Bhupinder Thakur wrote:
>> Hi Stefano,
>>
>> On 9 February 2017 at 05:40, Stefano Stabellini
>> wrote:
>> > On Wed, 8 Feb 2017, Bhupinder Thakur wrote:
>> >> Hi Julien,
>> >>
>> >> On 3 February 2017 at 1
>>> On 14.02.17 at 18:33, wrote:
> Hi,
>
> At 06:19 -0700 on 13 Feb (1486966797), Jan Beulich wrote:
>> The present way of setting this up is flawed: Leaving the I/O bitmap
>> pointer at zero means that the interrupt redirection bitmap lives
>> outside (ahead of) the allocated space of the TSS. S
Hi,
On 15 February 2017 at 13:45, Bhupinder Thakur
wrote:
> Hi Stefano,
>
> On 14 February 2017 at 03:14, Stefano Stabellini
> wrote:
>> On Mon, 13 Feb 2017, Bhupinder Thakur wrote:
>>> Hi Stefano,
>>>
>>> On 9 February 2017 at 05:40, Stefano Stabellini
>>> wrote:
>>> > On Wed, 8 Feb 2017,
>>> On 14.02.17 at 16:48, wrote:
> On 14/02/17 08:55, Jan Beulich wrote:
> On 13.02.17 at 19:26, wrote:
>>> On 13/02/17 13:19, Jan Beulich wrote:
---
TBD: Do we really want to re-init the TSS every time we are about to
use it? This can happen quite often during boot, espec
>>> On 14.02.17 at 17:04, wrote:
> On 13/02/17 12:36, Jan Beulich wrote:
> On 13.02.17 at 12:00, wrote:
>>> @@ -360,6 +361,21 @@ void paging_dump_vcpu_info(struct vcpu *v);
>>> int paging_set_allocation(struct domain *d, unsigned int pages,
>>>bool *preempted);
>>
>>> On 14.02.17 at 16:16, wrote:
> On 14/02/17 10:28, Jan Beulich wrote:
>> --- a/xen/arch/x86/hvm/vmx/vmcs.c
>> +++ b/xen/arch/x86/hvm/vmx/vmcs.c
>> @@ -552,6 +552,27 @@ static void vmx_load_vmcs(struct vcpu *v
>> local_irq_restore(flags);
>> }
>>
>> +void vmx_vmcs_reload(struct vcpu *v)
>>> On 14.02.17 at 16:26, wrote:
> On 14/02/17 10:29, Jan Beulich wrote:
>> @@ -2066,6 +2073,15 @@ static void __context_switch(void)
>> per_cpu(curr_vcpu, cpu) = n;
>> }
>>
>> +/*
>> + * Schedule tail *should* be a terminal function pointer, but leave a
>> bugframe
>> + * around just inc
This patch creates CAT and CDP feature document in doc/features/. It describes
key points to implement L3 CAT/CDP and L2 CAT which is described in details in
Intel SDM "INTEL® RESOURCE DIRECTOR TECHNOLOGY (INTEL® RDT) ALLOCATION
FEATURES".
Signed-off-by: Yi Sun
---
v8:
- change revision info
Hi all,
We plan to bring a new PSR (Platform Shared Resource) feature called
Intel L2 Cache Allocation Technology (L2 CAT) to Xen.
Besides the L2 CAT implementaion, we refactor the psr.c to make it more
flexible to add new features and fulfill the principle, open for extension
but closed for modi
To construct an extendible framework, we need analyze PSR features
and abstract the common things and feature specific things. Then,
encapsulate them into different data structures.
By analyzing PSR features, we can get below map.
+--+--+--+
->| Dom0 | Dom
The current cache allocation codes in psr.c do not consider
future features addition and are not friendly to extend.
To make psr.c be more flexible to add new features and fulfill
the program principle, open for extension but closed for
modification, we have to refactor the psr.c:
1. Analyze cache
This patch implements get value flow including L3 CAT callback
function.
It also changes domctl interface to make it more general.
With this patch, 'psr-cat-show' can work for L3 CAT but not for
L3 code/data which is implemented in patch "x86: refactor psr:
implement get value flow for CDP.".
Si
This patch implements the CPU init and free flow including L3 CAT
initialization and feature list free.
Signed-off-by: Yi Sun
---
v8:
- remove unused parameter of psr_cpu_prepare.
- add comments in cpu_fini_work.
- coding style fix.
---
xen/arch/x86/cpuid.c| 6 --
xen/a
This patch implements the Domain init/free and schedule flows.
Signed-off-by: Yi Sun
Reviewed-by: Konrad Rzeszutek Wilk
---
xen/arch/x86/psr.c | 62 +-
1 file changed, 61 insertions(+), 1 deletion(-)
diff --git a/xen/arch/x86/psr.c b/xen/arch
Continue with patch:
'x86: refactor psr: set value: assemble features value array'
We can try to find if there is a COS ID on which all features' COS registers
values are same as the array assembled before.
Signed-off-by: Yi Sun
---
xen/arch/x86/psr.c | 93 ++
This patch implements the CPU init and free flow for L2 CAT including
L2 CAT initialization callback function.
Signed-off-by: Yi Sun
---
xen/arch/x86/psr.c| 72 +++
xen/include/asm-x86/psr.h | 1 +
2 files changed, 73 insertions(+)
diff --git
As set value flow is the most complicated one in psr, it will be
divided to some patches to make things clearer. This patch
implements the set value framework to show a whole picture firstly.
It also changes domctl interface to make it more general.
To make the set value flow be general and can s
This patch implements get HW info flow for L2 CAT including L2 CAT callback
function.
Signed-off-by: Yi Sun
---
xen/arch/x86/psr.c | 16
xen/arch/x86/sysctl.c | 15 +++
xen/include/asm-x86/psr.h | 1 +
xen/include/public/sysctl.h | 6 ++
4 file
This patch implements get HW info flow including L3 CAT callback
function.
It also changes sysctl interface to make it more general.
With this patch, 'psr-hwinfo' can work for L3 CAT.
Signed-off-by: Yi Sun
Reviewed-by: Konrad Rzeszutek Wilk
---
xen/arch/x86/psr.c| 75 +
Continue with previous patch:
'x86: refactor psr: set value: implement cos id picking flow.'
We have got all features values and COS ID to set. Then, we write MSRs of all
features except the setting value is same as original value.
Till now, set value process is completed.
Signed-off-by: Yi Sun
This patch implements L3 CDP get value callback function.
With this patch, 'psr-cat-show' can work for L3 CDP.
Signed-off-by: Yi Sun
---
xen/arch/x86/psr.c | 16
1 file changed, 16 insertions(+)
diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c
index 72c9888..72ed923 100644
This patch implements the CPU init and free flow for CDP including L3 CDP
initialization callback function.
Signed-off-by: Yi Sun
---
xen/arch/x86/psr.c | 104 +
1 file changed, 98 insertions(+), 6 deletions(-)
diff --git a/xen/arch/x86/psr.c
Only can one COS ID be used by one domain at one time. That means all enabled
features' COS registers at this COS ID are valid for this domain at that time.
When user updates a feature's value, we need make sure all other features'
values are not affected. So, we firstly need assemble an array whi
This patch implements get HW info flow for CDP including L3 CDP callback
function.
It also changes sysctl function to make it work for CDP.
With this patch, 'psr-hwinfo' can work for L3 CDP.
Signed-off-by: Yi Sun
---
xen/arch/x86/psr.c| 18 ++
xen/arch/x86/sysctl.c | 24 +++
Continue with previous patch:
'x86: refactor psr: set value: implement cos finding flow.'
If fail to find a COS ID, we need pick a new COS ID for domain. Only COS ID
that ref[COS_ID] is 1 or 0 can be picked to input a new set feature values.
Signed-off-by: Yi Sun
---
xen/arch/x86/psr.c | 99 +++
This patch implements L3 CDP set value related callback functions.
With this patch, 'psr-cat-cbm-set' command can work for L3 CDP.
Signed-off-by: Yi Sun
---
v8:
- modify 'l3_cdp_write_msr' to 'void'.
---
xen/arch/x86/psr.c | 118 +
1 file
This patch implements L2 CAT get value callback function and
interface in domctl.
Signed-off-by: Yi Sun
---
xen/arch/x86/domctl.c | 7 +++
xen/arch/x86/psr.c | 12
xen/include/public/domctl.h | 1 +
3 files changed, 20 insertions(+)
diff --git a/xen/arch/x86/do
This patch adds L2 CAT description in related documents.
Signed-off-by: He Chen
Signed-off-by: Yi Sun
Acked-by: Wei Liu
---
docs/man/xl.pod.1.in | 25 ++---
docs/misc/xl-psr.markdown | 10 --
2 files changed, 30 insertions(+), 5 deletions(-)
diff --git a/docs/
This patch implements xl/xc changes to support get HW info
for L2 CAT.
'xl psr-hwinfo' is updated to show both L3 CAT and L2 CAT
info.
Example(on machine which only supports L2 CAT):
Cache Monitoring Technology (CMT):
Enabled : 0
Cache Allocation Technology (CAT): L2
Socket ID : 0
M
This patch implements changes in xl/xc changes to support
showing CBM of L2 CAT.
The new level option is introduced to original CAT showing
command in order to show CBM for specified level CAT.
- 'xl psr-cat-show' is updated to show CBM of a domain
according to input cache level.
Examples:
root
This patch implements the xl/xc changes to support set CBM
for L2 CAT.
The new level option is introduced to original CAT setting
command in order to set CBM for specified level CAT.
- 'xl psr-cat-cbm-set' is updated to set cache capacity
bitmasks(CBM) for a domain according to input cache level
This patch implements L2 CAT set value related callback functions
and domctl interface.
Signed-off-by: Yi Sun
---
v8:
- modify 'l2_cat_write_msr' to 'void'.
---
xen/arch/x86/domctl.c | 6 +++
xen/arch/x86/psr.c | 95 +
xen/inclu
>>> On 14.02.17 at 15:56, wrote:
> I tried to reproduce this, by limiting the amount of memory available to
> qemu using cgroups, but about 44MB of memory is enough to boot a guest
> (tried Ubuntu and Debian).
>
> How much memory did qemu try to use?
According to
kernel: Out of memory: Kill pro
Am Tue, 14 Feb 2017 20:27:15 +
schrieb Wei Liu :
> Better to just push to a branch for us to fetch.
That would be git://github.com/olafhering/xen.git#libreoffice
https://github.com/olafhering/xen/commits/libreoffice
Thanks,
Olaf
pgpgIrWZLs_Dh.pgp
Description: Digitale Signatur von OpenPG
> -Original Message-
> From: Stefano Stabellini [mailto:sstabell...@kernel.org]
> Sent: 14 February 2017 18:39
> To: Boris Ostrovsky
> Cc: Paul Durrant ; xen-de...@lists.xenproject.org;
> linux-ker...@vger.kernel.org; Stefano Stabellini ;
> Juergen Gross
> Subject: Re: [PATCH v3 2/3] xen/
flight 68561 distros-debian-squeeze real [real]
http://osstest.xs.citrite.net/~osstest/testlogs/logs/68561/
Failures :-/ but no regressions.
Regressions which are regarded as allowable (not blocking):
test-amd64-i386-i386-squeeze-netboot-pygrub 9 debian-di-install fail like 68536
test-amd64-amd
>>> On 14.02.17 at 18:25, wrote:
> 4. The security team will only issue an advisory if there is a known
> combination of software in which the vulnerability can be exploited.
Considering the following text, perhaps "may" would end up a little
less strict here than "can"? Or add "possibly"? Everyt
In this patch we add a function to close COLO kernel Proxy on secondary side.
Signed-off-by: Zhang Chen
---
tools/libxl/libxl_colo_restore.c | 8 ++--
tools/libxl/libxl_create.c | 8 ++--
tools/libxl/libxl_types.idl | 1 +
tools/libxl/xl_cmdimpl.c | 18 +
We use kernel colo proxy's way to get the checkpoint event
from qemu colo-compare.
Qemu colo-compare need add a API to support this(I will add this in qemu).
Signed-off-by: Zhang Chen
---
tools/libxl/libxl_colo.h | 2 +
tools/libxl/libxl_colo_proxy.c | 84 +
Add remus '-p' to enable userspace colo proxy(in qemu).
Signed-off-by: Zhang Chen
---
docs/man/xl.pod.1.in | 5 +
tools/libxl/libxl.h | 6 ++
tools/libxl/libxl_colo.h | 5 +
tools/libxl/libxl_colo_save.c | 2 ++
tools/libxl/libxl_types.idl | 17 +
We use params->colo_proxy_script to make do_domain_create()
doesn't take "colo_proxy_script" anymore.
Signed-off-by: Zhang Chen
---
tools/libxl/libxl_create.c | 17 ++---
1 file changed, 10 insertions(+), 7 deletions(-)
diff --git a/tools/libxl/libxl_create.c b/tools/libxl/libxl_cre
In this patch we close kernel COLO-Proxy on primary side.
Signed-off-by: Zhang Chen
---
tools/libxl/libxl_colo_proxy.c | 27 +++
tools/libxl/libxl_colo_save.c | 9 +++--
2 files changed, 34 insertions(+), 2 deletions(-)
diff --git a/tools/libxl/libxl_colo_proxy.c b
Qemu need this args to start userspace colo-proxy.
Signed-off-by: Zhang Chen
---
tools/libxl/libxl_dm.c | 34 ++
tools/libxl/libxl_nic.c | 27 +++
tools/libxl/libxl_types.idl | 15 ++-
tools/libxl/xl_cmdimpl.c| 27 +
Qemu need this args to start userspace colo-proxy.
Signed-off-by: Zhang Chen
---
tools/libxl/libxl_dm.c | 98 +
tools/libxl/libxl_nic.c | 78
tools/libxl/libxl_types.idl | 31 +-
tools/libxl/xl_
Because of some reason, We no longer support COLO kernel proxy.
So we send this patch set to make Xen use userspace colo-proxy in qemu.
Below is a COLO userspace proxy ascii figure:
Primary qemu
Secondary qemu
+--
flight 105808 ovmf real [real]
http://logs.test-lab.xenproject.org/osstest/logs/105808/
Perfect :-)
All tests in this flight passed as required
version targeted for testing:
ovmf 5e9e151c2061cc10e5aa9f41c6f1d7d1b865954e
baseline version:
ovmf 5b97eb4c35316cbe8235a
>>> On 15.02.17 at 00:21, wrote:
> On 14/02/2017 22:47, Tamas K Lengyel wrote:
>> (XEN) Switched to APIC driver x2apic_cluster.
>> (XEN) XSM Framework v1.0.0 initialized
>> (XEN) Flask: 128 avtab hash slots, 394 rules.
>> (XEN) Flask: 128 avtab hash slots, 394 rules.
>> (XEN) Flask: 5 users, 3 ro
Block backends defined with -drive if=ide are meant to be picked up by
machine initialization code: a suitable frontend gets created and
wired up automatically.
if=ide drives not picked up that way can still be used with -device as
if they had if=none, but that's unclean and best avoided. Unused
On Thu, Feb 9, 2017 at 1:58 PM, Dario Faggioli
wrote:
> Information we currently print for idle pCPUs is
I take it you meant "idle vCPUs here"? If so I can fix that up on check-in.
Other than that:
Reviewed-by: George Dunlap
___
Xen-devel mailing l
On Thu, Feb 9, 2017 at 1:58 PM, Dario Faggioli
wrote:
> Since we are doing cpumask manipulation already, clear a bit
> in the mask at once. Doing that will save us an if, later in
> the code.
>
> No functional change intended.
>
> Signed-off-by: Dario Faggioli
Reviewed-by: George Dunlap
> ---
>>> On 14.02.17 at 19:38, wrote:
> --- a/xen/arch/x86/boot/head.S
> +++ b/xen/arch/x86/boot/head.S
> @@ -394,10 +394,18 @@ __start:
>
> /* EFI IA-32 platforms are not supported. */
> cmpl$MULTIBOOT2_TAG_TYPE_EFI32,MB2_tag_type(%ecx)
> +/*
> + * Here we should
On Tue, 2017-02-14 at 03:28 -0700, Jan Beulich wrote:
> When __context_switch() is being bypassed during original context
> switch handling, the vCPU "owning" the VMCS partially loses control of
> it: It will appear non-running to remote CPUs, and hence their attempt
> to pause the owning vCPU will
On Wed, 2017-02-15 at 10:17 +, George Dunlap wrote:
> On Thu, Feb 9, 2017 at 1:58 PM, Dario Faggioli
> wrote:
> >
> > Information we currently print for idle pCPUs is
>
> I take it you meant "idle vCPUs here"?
>
Sort-of. What I actually meant is that we print info about the idle
vCPUs for
On Thu, Feb 9, 2017 at 1:58 PM, Dario Faggioli
wrote:
> Most of the comments describing the meaning of the
> vCPU flags used by the scheduler miss the 'wings' (or
> have other minor style issues).
>
> Also, use 1U (instead of 1) as the base of shiftings.
>
> No functional change intended.
>
> Sign
This includes support for AVX counterparts of them as well as a few
later SSE additions (basically covering the entire 0f-prefixed opcode
space, but not the 0f38 and 0f3a ones, nor 3dnow).
1: catch exceptions occurring in stubs
2: support most memory accessing MMX/SSE{,2,3} insns
3: support MMX
On Thu, Feb 9, 2017 at 3:33 PM, Dario Faggioli
wrote:
> On Thu, 2017-02-09 at 07:36 -0700, Jan Beulich wrote:
>> > > > On 09.02.17 at 14:58, wrote:
>> > +/* CPU to runq_id macro */
>> > +static always_inline int c2r(const struct scheduler *ops, unsigned
>> > cpu)
>> > +{
>> > +return (csched2
At 01:13 -0700 on 15 Feb (1487121231), Jan Beulich wrote:
> >>> On 14.02.17 at 18:35, wrote:
> > At 06:37 -0700 on 13 Feb (1486967832), Jan Beulich wrote:
> >> >>> On 13.02.17 at 14:19, wrote:
> >> > -tss = mem_alloc(128, 128);
> >> > -memset(tss, 0, 128);
> >> > +tss = mem_alloc(TSS_
>>> On 15.02.17 at 11:27, wrote:
> This is what I'm getting during the original test case (32 VMs reboot):
>
> (XEN) [ 1407.789329] Watchdog timer detects that CPU12 is stuck!
> (XEN) [ 1407.795726] [ Xen-4.6.1-xs-local x86_64 debug=n Not tainted
> ]
> (XEN) [ 1407.803774] CPU:12
George,
I noticed that the blog post does not contain a link to the xen-devel@
discussion. I will add it
Lars
> On 15 Feb 2017, at 09:44, Jan Beulich wrote:
>
On 14.02.17 at 18:25, wrote:
>> 4. The security team will only issue an advisory if there is a known
>> combination of software in
flight 105804 xen-unstable real [real]
http://logs.test-lab.xenproject.org/osstest/logs/105804/
Failures :-/ but no regressions.
Tests which are failing intermittently (not blocking):
test-amd64-i386-libvirt-xsm 3 host-install(3) broken in 105799 pass in 105804
test-amd64-amd64-xl-qemuu-debian
Before adding more use of stubs cloned from decoded guest insns, guard
ourselves against mistakes there: Should an exception (with the
noteworthy exception of #PF) occur inside the stub, forward it to the
guest.
Since the exception fixup table entry can't encode the address of the
faulting insn it
This aims at covering most MMX/SSEn/AVX instructions in the 0x0f-escape
space with memory operands. Not covered here are irregular moves,
converts, and {,U}COMIS{S,D} (modifying EFLAGS).
Note that the distinction between simd_*_fp isn't strictly needed, but
I've kept them as separate entries since
Previously supported insns are being converted to the new model, and
several new ones are being added.
To keep the stub handling reasonably simple, integrate SET_SSE_PREFIX()
into copy_REX_VEX(), at once switching the stubs to use an empty REX
prefix instead of a double DS: one (no byte registers
Note that other than most scalar instructions, vcvt{,t}s{s,d}2si do #UD
when VEX.l is set on at least some Intel models. To be on the safe
side, implement the most restrictive mode here for now when emulating
an Intel CPU, and simply clear the bit when emulating an AMD one.
Signed-off-by: Jan Beul
Signed-off-by: Jan Beulich
---
v3: Ignore VEX.l. Add fic.exn_raised constraint to invoke_stub() use.
v2: Add missing RET to stub. Generate #UD (instead of simply failing)
when VEX.l is disallowed.
--- a/xen/arch/x86/x86_emulate/x86_emulate.c
+++ b/xen/arch/x86/x86_emulate/x86_emulate.c
@@ -24
Signed-off-by: Jan Beulich
---
v3: Re-base.
--- a/tools/fuzz/x86_instruction_emulator/x86-insn-emulator-fuzzer.c
+++ b/tools/fuzz/x86_instruction_emulator/x86-insn-emulator-fuzzer.c
@@ -660,7 +660,7 @@ int LLVMFuzzerTestOneInput(const uint8_t
};
int rc;
-stack_exec = emul_test_mak
This involves fixing a decode bug: VEX encoded insns aren't necessarily
followed by a ModR/M byte.
Signed-off-by: Jan Beulich
---
v3: Simplify handling of extrq/insertq register forms. Use simd_0f_xmm
label.
v2: Correct {,v}pextrw operand descriptor.
--- a/xen/arch/x86/x86_emulate/x86_emulat
Specifying an empty cdrom device will result in a Xenstore entry
params = aio:(null)
as the physical device path isn't existing. This lets a domain booted
via OVMF hang as OVMF is checking for "aio:" only in order to detect
the empty cdrom case.
Use an empty string for the physical device path i
... as the only post-SSE2 move insn.
Signed-off-by: Jan Beulich
---
v3: Re-base.
v2: Re-base.
--- a/tools/tests/x86_emulator/test_x86_emulator.c
+++ b/tools/tests/x86_emulator/test_x86_emulator.c
@@ -2380,6 +2380,74 @@ int main(int argc, char **argv)
else
printf("skipped\n");
+
Both the build logic and the invocation have their blowfish specific
aspects abstracted out here. Additionally
- run native execution (if suitable) first (as that one failing
suggests a problem with the to be tested code itself, in which case
having the emulator have a go over it is kind of poi
... and their AVX equivalents. Note that a few instructions aren't
covered (yet), but those all fall into common pattern groups, so I
would hope that for now we can do with what is there.
MMX insns aren't being covered at all, as they're not easy to deal
with: The compiler refuses to emit such for
On Wed, 2017-02-15 at 04:00 -0700, Jan Beulich wrote:
> > > > On 15.02.17 at 11:27, wrote:
> >
> > This is what I'm getting during the original test case (32 VMs reboot):
> >
> > (XEN) [ 1407.789329] Watchdog timer detects that CPU12 is stuck!
> > (XEN) [ 1407.795726] [ Xen-4.6.1-xs-local x
flight 105813 xen-unstable-coverity real [real]
http://logs.test-lab.xenproject.org/osstest/logs/105813/
Perfect :-)
All tests in this flight passed as required
version targeted for testing:
xen bdbc25b8722cc1e3921858530f8ac484892156d3
baseline version:
xen 6f6d
This being a strict (MMX register only) subset of SSE, we can simply
adjust the respective checks while making the new predicate look at
both flags.
Signed-off-by: Jan Beulich
---
v3: New.
--- a/xen/arch/x86/x86_emulate/x86_emulate.c
+++ b/xen/arch/x86/x86_emulate/x86_emulate.c
@@ -1399,6 +1399,
Convert the few existing opcodes so far supported.
Signed-off-by: Jan Beulich
---
v3: New.
--- a/xen/arch/x86/x86_emulate/x86_emulate.c
+++ b/xen/arch/x86/x86_emulate/x86_emulate.c
@@ -43,6 +43,8 @@
#define SrcMask (7<<3)
/* Generic ModRM decode. */
#define ModRM (1<<6)
+/* vSIB add
... and their AVX equivalents.
Signed-off-by: Jan Beulich
---
v3: New.
--- a/xen/arch/x86/x86_emulate/x86_emulate.c
+++ b/xen/arch/x86/x86_emulate/x86_emulate.c
@@ -343,6 +343,8 @@ static const struct {
uint8_t two_op:1;
uint8_t vsib:1;
} ext0f38_table[256] = {
+[0x00 ... 0x0b] =
... and their AVX equivalents.
Signed-off-by: Jan Beulich
---
v3: New.
--- a/xen/arch/x86/x86_emulate/x86_emulate.c
+++ b/xen/arch/x86/x86_emulate/x86_emulate.c
@@ -214,6 +214,12 @@ enum simd_opsize {
* - 32 bits with prefix F3 (scalar)
*/
simd_single_fp,
+/*
+ * Scalar
... and its AVX equivalent.
Signed-off-by: Jan Beulich
---
v3: New.
--- a/xen/arch/x86/x86_emulate/x86_emulate.c
+++ b/xen/arch/x86/x86_emulate/x86_emulate.c
@@ -387,6 +387,7 @@ static const struct {
[0x22] = { .simd_size = simd_none },
[0x40 ... 0x41] = { .simd_size = simd_packed_fp }
... and their AVX equivalents.
Signed-off-by: Jan Beulich
---
v3: New.
--- a/tools/tests/x86_emulator/test_x86_emulator.c
+++ b/tools/tests/x86_emulator/test_x86_emulator.c
@@ -2542,6 +2542,149 @@ int main(int argc, char **argv)
else
printf("skipped\n");
+printf("%-40s", "Tes
... and their AVX equivalents.
Signed-off-by: Jan Beulich
---
v3: New.
--- a/xen/arch/x86/x86_emulate/x86_emulate.c
+++ b/xen/arch/x86/x86_emulate/x86_emulate.c
@@ -362,6 +362,8 @@ static const struct {
[0x37 ... 0x3f] = { .simd_size = simd_packed_int },
[0x40] = { .simd_size = simd_pa
Signed-off-by: Jan Beulich
---
v3: New.
--- a/xen/arch/x86/x86_emulate/x86_emulate.c
+++ b/xen/arch/x86/x86_emulate/x86_emulate.c
@@ -362,6 +362,7 @@ static const struct {
[0x37 ... 0x3f] = { .simd_size = simd_packed_int },
[0x40] = { .simd_size = simd_packed_int },
[0x41] = { .sim
At 01:18 -0700 on 15 Feb (1487121525), Jan Beulich wrote:
> >>> On 14.02.17 at 18:33, wrote:
> >> TBD: Do we really want to re-init the TSS every time we are about to
> >> use it?
> >
> > No - I think we should init it when the guest writes the param(s) and
> > leave it at that. Hvmloader m
>>> On 15.02.17 at 12:13, wrote:
> On Wed, 2017-02-15 at 04:00 -0700, Jan Beulich wrote:
>> Similarly, when __context_switch() is being bypassed also on the second
>> (switch-in) path, VMCS ownership may have been lost and hence needs
>> re-establishing. Since there's no existing hook to put this
On 15/02/17 11:06, Jan Beulich wrote:
> --- a/xen/arch/x86/x86_emulate/x86_emulate.c
> +++ b/xen/arch/x86/x86_emulate/x86_emulate.c
> @@ -604,14 +604,42 @@ do{ asm volatile (
> #define __emulate_1op_8byte(_op, _dst, _eflags)
> #endif /* __i386__ */
>
> +#ifdef __XEN__
> +# define invoke_stub(pr
On 15/02/17 08:37, Jan Beulich wrote:
On 14.02.17 at 16:16, wrote:
>> On 14/02/17 10:28, Jan Beulich wrote:
>>> --- a/xen/arch/x86/hvm/vmx/vmcs.c
>>> +++ b/xen/arch/x86/hvm/vmx/vmcs.c
>>> @@ -552,6 +552,27 @@ static void vmx_load_vmcs(struct vcpu *v
>>> local_irq_restore(flags);
>>> }
>
On 15/02/17 08:42, Jan Beulich wrote:
On 14.02.17 at 16:26, wrote:
>> On 14/02/17 10:29, Jan Beulich wrote:
>>> @@ -2066,6 +2073,15 @@ static void __context_switch(void)
>>> per_cpu(curr_vcpu, cpu) = n;
>>> }
>>>
>>> +/*
>>> + * Schedule tail *should* be a terminal function pointer, b
>>> On 15.02.17 at 12:21, wrote:
> At 01:18 -0700 on 15 Feb (1487121525), Jan Beulich wrote:
>> >>> On 14.02.17 at 18:33, wrote:
>> >> TBD: Do we really want to re-init the TSS every time we are about to
>> >> use it?
>> >
>> > No - I think we should init it when the guest writes the param(
>>> On 15.02.17 at 11:27, wrote:
> This is what I'm getting during the original test case (32 VMs reboot):
>
> (XEN) [ 1407.789329] Watchdog timer detects that CPU12 is stuck!
> (XEN) [ 1407.795726] [ Xen-4.6.1-xs-local x86_64 debug=n Not tainted
> ]
> (XEN) [ 1407.803774] CPU:12
>>> On 15.02.17 at 12:34, wrote:
> On 15/02/17 08:42, Jan Beulich wrote:
> On 14.02.17 at 16:26, wrote:
>>> On 14/02/17 10:29, Jan Beulich wrote:
@@ -2066,6 +2073,15 @@ static void __context_switch(void)
per_cpu(curr_vcpu, cpu) = n;
}
+/*
+ * Schedule tai
On Wed, 2017-02-15 at 04:39 -0700, Jan Beulich wrote:
> > > > On 15.02.17 at 11:27, wrote:
> >
> > This is what I'm getting during the original test case (32 VMs reboot):
> >
> > (XEN) [ 1407.789329] Watchdog timer detects that CPU12 is stuck!
> > (XEN) [ 1407.795726] [ Xen-4.6.1-xs-local x
>>> On 15.02.17 at 12:27, wrote:
> On 15/02/17 11:06, Jan Beulich wrote:
>> --- a/xen/arch/x86/x86_emulate/x86_emulate.c
>> +++ b/xen/arch/x86/x86_emulate/x86_emulate.c
>> @@ -604,14 +604,42 @@ do{ asm volatile (
>> #define __emulate_1op_8byte(_op, _dst, _eflags)
>> #endif /* __i386__ */
>>
>>
>>> On 15.02.17 at 12:48, wrote:
> On Wed, 2017-02-15 at 04:39 -0700, Jan Beulich wrote:
>> > > > On 15.02.17 at 11:27, wrote:
>> > (XEN) [ 1408.075638] Xen call trace:
>> > (XEN) [ 1408.079322][] vmx_vmcs_reload+0x32/0x50
>> > (XEN) [ 1408.086303][] context_switch+0x85d/0xeb0
>> > (XEN)
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
Xen Security Advisory XSA-207
version 2
memory leak when destroying guest without PT devices
UPDATES IN VERSION 2
Public release.
ISSUE DESCRIPTION
=
C
This run is configured for baseline tests only.
flight 68562 ovmf real [real]
http://osstest.xs.citrite.net/~osstest/testlogs/logs/68562/
Perfect :-)
All tests in this flight passed as required
version targeted for testing:
ovmf 5e9e151c2061cc10e5aa9f41c6f1d7d1b865954e
baseline v
>>> On 15.02.17 at 12:55, wrote:
On 15.02.17 at 12:48, wrote:
>> On Wed, 2017-02-15 at 04:39 -0700, Jan Beulich wrote:
>>> > > > On 15.02.17 at 11:27, wrote:
>>> > (XEN) [ 1408.075638] Xen call trace:
>>> > (XEN) [ 1408.079322][] vmx_vmcs_reload+0x32/0x50
>>> > (XEN) [ 1408.086303][
>>> On 15.02.17 at 11:27, wrote:
> This is what I'm getting during the original test case (32 VMs reboot):
>
> (XEN) [ 1407.789329] Watchdog timer detects that CPU12 is stuck!
> (XEN) [ 1407.795726] [ Xen-4.6.1-xs-local x86_64 debug=n Not tainted
> ]
Hmm, this was with a non-debug bu
On Wed, 2017-02-15 at 06:03 -0700, Jan Beulich wrote:
> > > > On 15.02.17 at 12:55, wrote:
> > > > > On 15.02.17 at 12:48, wrote:
> > >
> > > On Wed, 2017-02-15 at 04:39 -0700, Jan Beulich wrote:
> > > > > > > On 15.02.17 at 11:27, wrote:
> > > > >
> > > > > (XEN) [ 1408.075638] Xen call trace
Hi all,
I am kind of stuck on this one and wanted to pick up the discussion again.
Apologies that it took so long.
To to summarise, we all are agreed on most sections of the proposal,
with the exception of decision making across projects. One option is to
just apply what we agreed on and leave t
On Thu, Feb 9, 2017 at 1:58 PM, Dario Faggioli
wrote:
> There is no reason for having pretty much all of the
> functions whose names begin with double underscores
> ('__') to actually look like that.
>
> In fact, that is misleading and makes the code hard
> to read and understand. So, remove the '
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