On Mon, 2017-05-15 at 15:32 +0100, George Dunlap wrote:
> On Mon, May 15, 2017 at 2:35 PM, Andrew Cooper
> wrote:
> > On systems with this number of in-flight interrupts, trying to
> > track
> > "who got what interrupt" for priority
> > boosting purposes is a waste of
> > time, as we spend ages ta
On Mon, May 15, 2017 at 2:35 PM, Andrew Cooper
wrote:
> On 15/05/17 11:27, George Dunlap wrote:
>> On Fri, May 12, 2017 at 12:05 PM, Andrew Cooper
>> wrote:
>>> Citrix Netscalar SDX boxes have more MSI-X interrupts than fit in the
>>> cumulative IDTs of a top end dual-socket Xeon server systems.
On 15/05/17 11:27, George Dunlap wrote:
> On Fri, May 12, 2017 at 12:05 PM, Andrew Cooper
> wrote:
>> Citrix Netscalar SDX boxes have more MSI-X interrupts than fit in the
>> cumulative IDTs of a top end dual-socket Xeon server systems. Some of
>> the device drivers are purposefully modelled to u
On Fri, May 12, 2017 at 12:05 PM, Andrew Cooper
wrote:
> Citrix Netscalar SDX boxes have more MSI-X interrupts than fit in the
> cumulative IDTs of a top end dual-socket Xeon server systems. Some of
> the device drivers are purposefully modelled to use fewer interrupts
> than they otherwise would
On 27/04/17 08:08, Jan Beulich wrote:
On 26.04.17 at 19:11, wrote:
>> On 18/04/17 07:24, Tian, Kevin wrote:
From: Gao, Chao
Sent: Monday, April 17, 2017 4:14 AM
On Tue, Apr 11, 2017 at 02:21:07AM -0600, Jan Beulich wrote:
On 11.04.17 at 02:59, wrote:
>> As yo
>>> On 26.04.17 at 19:11, wrote:
> On 18/04/17 07:24, Tian, Kevin wrote:
>>> From: Gao, Chao
>>> Sent: Monday, April 17, 2017 4:14 AM
>>>
>>> On Tue, Apr 11, 2017 at 02:21:07AM -0600, Jan Beulich wrote:
>>> On 11.04.17 at 02:59, wrote:
> As you know, with VT-d PI enabled, hardware can dir
On 18/04/17 07:24, Tian, Kevin wrote:
>> From: Gao, Chao
>> Sent: Monday, April 17, 2017 4:14 AM
>>
>> On Tue, Apr 11, 2017 at 02:21:07AM -0600, Jan Beulich wrote:
>> On 11.04.17 at 02:59, wrote:
As you know, with VT-d PI enabled, hardware can directly deliver external
interrupts to
>>> On 18.04.17 at 05:41, wrote:
> On Tue, Apr 18, 2017 at 02:13:36AM -0600, Jan Beulich wrote:
> On 16.04.17 at 22:13, wrote:
>>> 3. Like what we do in struct irq_guest_action_t, can we limit the
>>> maximum of entry we support in the list. With this approach, during
>>> domain creation, we
On Tue, Apr 18, 2017 at 02:13:36AM -0600, Jan Beulich wrote:
On 16.04.17 at 22:13, wrote:
>> 3. Like what we do in struct irq_guest_action_t, can we limit the
>> maximum of entry we support in the list. With this approach, during
>> domain creation, we calculate the available entries and comp
>>> On 16.04.17 at 22:13, wrote:
> 3. Like what we do in struct irq_guest_action_t, can we limit the
> maximum of entry we support in the list. With this approach, during
> domain creation, we calculate the available entries and compare with
> the domain's vCPU number to decide whether the domain
On Tue, Apr 18, 2017 at 02:24:05PM +0800, Tian, Kevin wrote:
>> From: Gao, Chao
>> Sent: Monday, April 17, 2017 4:14 AM
>>
>> On Tue, Apr 11, 2017 at 02:21:07AM -0600, Jan Beulich wrote:
>> On 11.04.17 at 02:59, wrote:
>> 3. Like what we do in struct irq_guest_action_t, can we limit the
>> m
> From: Gao, Chao
> Sent: Monday, April 17, 2017 4:14 AM
>
> On Tue, Apr 11, 2017 at 02:21:07AM -0600, Jan Beulich wrote:
> On 11.04.17 at 02:59, wrote:
> >> As you know, with VT-d PI enabled, hardware can directly deliver external
> >> interrupts to guest without any VMM intervention. It wi
On Tue, Apr 11, 2017 at 02:21:07AM -0600, Jan Beulich wrote:
On 11.04.17 at 02:59, wrote:
>> As you know, with VT-d PI enabled, hardware can directly deliver external
>> interrupts to guest without any VMM intervention. It will reduces overall
>> interrupt latency to guest and reduces overhea
>>> On 11.04.17 at 02:59, wrote:
> As you know, with VT-d PI enabled, hardware can directly deliver external
> interrupts to guest without any VMM intervention. It will reduces overall
> interrupt latency to guest and reduces overheads otherwise incurred by the
> VMM for virtualizing interrupts. I
14 matches
Mail list logo
