On Thu, 2 Nov 2017, Andre Przywara wrote:
> (CC:ing some KVM/ARM folks involved in the VGIC)
>
> starting with the addition of the ITS support we were seeing more and
> more issues with the current implementation of our ARM Generic Interrupt
> Controller (GIC) emulation, th
Hi,
On 01/11/17 21:54, Stefano Stabellini wrote:
> On Wed, 1 Nov 2017, Andre Przywara wrote:
>> Hi Stefano,
>>
>>
>> On 01/11/17 01:58, Stefano Stabellini wrote:
>>> On Wed, 11 Oct 2017, Andre Przywara wrote:
>>
>> many thanks for going through all of this!
>
> No problems, and thanks for your wo
On Wed, Nov 1, 2017 at 10:54 PM, Stefano Stabellini
wrote:
[...]
>
>> > The suggestion of using this model in Xen was made in the past already.
>> > I always objected for the reason that we don't actually know how many
>> > LRs the hardware provides, potentially very many, and it is expensive
>>
On Wed, Nov 1, 2017 at 10:15 AM, Andre Przywara
wrote:
> Hi,
>
> On 01/11/17 04:31, Christoffer Dall wrote:
>> On Wed, Nov 1, 2017 at 9:58 AM, Stefano Stabellini
>> wrote:
>>
>> []
>
> Christoffer, many thanks for answering this!
> I think we have a lot of assumptions about the whole VGIC lif
On Wed, 1 Nov 2017, Andre Przywara wrote:
> Hi Stefano,
>
>
> On 01/11/17 01:58, Stefano Stabellini wrote:
> > On Wed, 11 Oct 2017, Andre Przywara wrote:
>
> many thanks for going through all of this!
No problems, and thanks for your work and for caring about doing the
best thing for the projec
Hi Christoffer,
On 12/10/17 13:05, Christoffer Dall wrote:
> Hi Andre,
>
> On Wed, Oct 11, 2017 at 03:33:03PM +0100, Andre Przywara wrote:
>> Hi,
>>
>> (CC:ing some KVM/ARM folks involved in the VGIC)
>
> Very nice writeup!
>
> I added a bunch of comments, mostly for the writing and clarity, I
Hi Stefano,
On 01/11/17 01:58, Stefano Stabellini wrote:
> On Wed, 11 Oct 2017, Andre Przywara wrote:
many thanks for going through all of this!
>> (CC:ing some KVM/ARM folks involved in the VGIC)
>>
>> starting with the addition of the ITS support we were seeing more and
>> more issues with th
Hi,
On 01/11/17 04:31, Christoffer Dall wrote:
> On Wed, Nov 1, 2017 at 9:58 AM, Stefano Stabellini
> wrote:
>
> []
Christoffer, many thanks for answering this!
I think we have a lot of assumptions about the whole VGIC life cycle
floating around, but it would indeed be good to get some numb
On Wed, Nov 1, 2017 at 9:58 AM, Stefano Stabellini
wrote:
[]
>
>> ### List register management
>>
>> A list register (LR) holds the state of a virtual interrupt, which will
>> be used by the GIC hardware to simulate an IRQ life cycle for a guest.
>> Each GIC hardware implementation can choos
On Wed, 11 Oct 2017, Andre Przywara wrote:
> Hi,
>
> (CC:ing some KVM/ARM folks involved in the VGIC)
>
> starting with the addition of the ITS support we were seeing more and
> more issues with the current implementation of our ARM Generic Interrupt
> Controller (GIC) emulation, the VGIC.
> Amon
Hi Andre,
On Wed, Oct 11, 2017 at 03:33:03PM +0100, Andre Przywara wrote:
> Hi,
>
> (CC:ing some KVM/ARM folks involved in the VGIC)
Very nice writeup!
I added a bunch of comments, mostly for the writing and clarity, I hope
it helps.
>
> starting with the addition of the ITS support we were s
Hi,
On 11/10/17 15:33, Andre Przywara wrote:
> Hi,
>
> (CC:ing some KVM/ARM folks involved in the VGIC)
>
> starting with the addition of the ITS support we were seeing more and
> more issues with the current implementation of our ARM Generic Interrupt
> Controller (GIC) emulation, the VGIC.
> A
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