At 14:03 + on 27 Feb (1488204194), Andrew Cooper wrote:
> Some bits are unconditionally reserved in pagetable entries, or reserved
> because of alignment restrictions. Other bits are reserved because of control
> register configuration.
>
> Introduce helpers which take an individual vcpu and
On 02/03/17 15:09, Tim Deegan wrote:
> At 14:17 + on 02 Mar (1488464221), Andrew Cooper wrote:
>> On 02/03/17 14:12, Tim Deegan wrote:
>>> At 14:03 + on 27 Feb (1488204194), Andrew Cooper wrote:
+static inline bool guest_has_pse36(const struct vcpu *v)
+{
+ /* No support
At 14:17 + on 02 Mar (1488464221), Andrew Cooper wrote:
> On 02/03/17 14:12, Tim Deegan wrote:
> > At 14:03 + on 27 Feb (1488204194), Andrew Cooper wrote:
> >> +static inline bool guest_has_pse36(const struct vcpu *v)
> >> +{
> >> + /* No support for 2-level PV guests. */
> >> +retu
On 02/03/17 14:12, Tim Deegan wrote:
> At 14:03 + on 27 Feb (1488204194), Andrew Cooper wrote:
>> +static inline bool guest_has_pse36(const struct vcpu *v)
>> +{
>> + /* No support for 2-level PV guests. */
>> +return is_pv_vcpu(v) ? 0 : paging_mode_hap(v->domain);
>> +}
> Should this c
At 14:03 + on 27 Feb (1488204194), Andrew Cooper wrote:
> +static inline bool guest_has_pse36(const struct vcpu *v)
> +{
> + /* No support for 2-level PV guests. */
> +return is_pv_vcpu(v) ? 0 : paging_mode_hap(v->domain);
> +}
Should this check the CPUID policy to see whether PSE36 is
On 01/03/17 15:57, Jan Beulich wrote:
On 27.02.17 at 15:03, wrote:
>> -static inline int
>> -guest_supports_1G_superpages(struct vcpu *v)
>> +static inline bool guest_has_pse36(const struct vcpu *v)
>> +{
>> + /* No support for 2-level PV guests. */
>> +return is_pv_vcpu(v) ? 0 : pagi
>>> On 27.02.17 at 15:03, wrote:
> -static inline int
> -guest_supports_1G_superpages(struct vcpu *v)
> +static inline bool guest_has_pse36(const struct vcpu *v)
> +{
> + /* No support for 2-level PV guests. */
> +return is_pv_vcpu(v) ? 0 : paging_mode_hap(v->domain);
Considering the retu
