Hi Vijay,
On 05/12/2014 00:46, Vijay Kilari wrote:
> Yes, this is the behaviour that Iam seeing. In Linux, uart driver
masks TXI interrupt
in IMSC if buffer is empty. However in xen, this scenario is not
handled. This is the reason why cpu does not come out of uart irq
routine if TX interrupt i
Hi Tim,
On Thu, Dec 4, 2014 at 9:10 PM, Tim Deegan wrote:
> At 13:51 + on 04 Dec (1417697518), Julien Grall wrote:
>> On 04/12/14 03:50, Vijay Kilari wrote:
>> > Hi Tim,
>>
>> Hi Vijay,
>>
>> > I see that on uart interrupt, ICR is written to clear the all
>> > interrupts except TX, RX and RX
At 13:51 + on 04 Dec (1417697518), Julien Grall wrote:
> On 04/12/14 03:50, Vijay Kilari wrote:
> > Hi Tim,
>
> Hi Vijay,
>
> > I see that on uart interrupt, ICR is written to clear the all
> > interrupts except TX, RX and RX timeout. With this, cpu always finds
> > TX/RX is active and never
On 04/12/14 03:50, Vijay Kilari wrote:
> Hi Tim,
Hi Vijay,
> I see that on uart interrupt, ICR is written to clear the all
> interrupts except TX, RX and RX timeout. With this, cpu always finds
> TX/RX is active and never
> comes out of the loop.
FWIW, the PL011 serial code has been copied from
Hi Tim,
I see that on uart interrupt, ICR is written to clear the all
interrupts except TX, RX and RX timeout. With this, cpu always finds
TX/RX is active and never
comes out of the loop.
With the below changes, TX, RX & RTI are cleared before handling this
interrupts.
Is my observation is corre
