On 03/31/2017 01:32 PM, Meng Xu wrote:
> Hi Boris,
>
> On Fri, Mar 31, 2017 at 12:01 PM, Boris Ostrovsky
> wrote:
When I program the general performance counter to trigger an overflow
interrupt, I set the following bits for the event selector register
and run a task to generate the
Hi Boris,
On Fri, Mar 31, 2017 at 12:01 PM, Boris Ostrovsky
wrote:
>
>>> When I program the general performance counter to trigger an overflow
>>> interrupt, I set the following bits for the event selector register
>>> and run a task to generate the L3 cache cache miss.
>>> FLAG_ENABLE: 0x40U
>> When I program the general performance counter to trigger an overflow
>> interrupt, I set the following bits for the event selector register
>> and run a task to generate the L3 cache cache miss.
>> FLAG_ENABLE: 0x40UL
>> FLAG_INT:0x10UL
>> FLAG_USR: 0x01UL
>> L3_ALLMISS_EVENT
>>> On 31.03.17 at 17:41, wrote:
> I'm wondering:
> How does Xen (vpmu) handle the general performance counter's overflow
> interrupt?
> Could you point me to the function handler, if Xen does handle it?
Two simple steps take you there: grep for LVTPC to find which vector
is being used (PMU_APIC
[Sorry, I cc.ed Quan's previous email at Intel. Change to his current email.]
On Fri, Mar 31, 2017 at 11:41 AM, Meng Xu wrote:
> Hi Jan and Boris,
>
> I'm Meng Xu from the University of Pennsylvania.
>
> I'm wondering:
> How does Xen (vpmu) handle the general performance counter's overflow
> int
Hi Jan and Boris,
I'm Meng Xu from the University of Pennsylvania.
I'm wondering:
How does Xen (vpmu) handle the general performance counter's overflow interrupt?
Could you point me to the function handler, if Xen does handle it?
---What I want to achieve---
I'm looking at the real-time performa
