On 20/08/15 10:34, Tim Deegan wrote:
At 17:36 +0100 on 19 Aug (1440005801), Ben Catterall wrote:
On 19/08/15 16:43, Tim Deegan wrote:
At 16:04 +0100 on 19 Aug (144260), Ben Catterall wrote:
I've hit a blocker on getting this working for AMD's SVM and would
appreciate any thoughts. Hopefull
On 20/08/15 10:34, Tim Deegan wrote:
At 17:36 +0100 on 19 Aug (1440005801), Ben Catterall wrote:
On 19/08/15 16:43, Tim Deegan wrote:
At 16:04 +0100 on 19 Aug (144260), Ben Catterall wrote:
I've hit a blocker on getting this working for AMD's SVM and would
appreciate any thoughts. Hope
At 17:36 +0100 on 19 Aug (1440005801), Ben Catterall wrote:
>
>
> On 19/08/15 16:43, Tim Deegan wrote:
> > At 16:04 +0100 on 19 Aug (144260), Ben Catterall wrote:
> >> I've hit a blocker on getting this working for AMD's SVM and would
> >> appreciate any thoughts. Hopefully I've missed a much
On 19/08/15 16:43, Tim Deegan wrote:
At 16:04 +0100 on 19 Aug (144260), Ben Catterall wrote:
I've hit a blocker on getting this working for AMD's SVM and would
appreciate any thoughts. Hopefully I've missed a much simpler way of
doing this or I've missed something!
So, AMD and Intel diffe
At 16:04 +0100 on 19 Aug (144260), Ben Catterall wrote:
> I've hit a blocker on getting this working for AMD's SVM and would
> appreciate any thoughts. Hopefully I've missed a much simpler way of
> doing this or I've missed something!
>
> So, AMD and Intel differ in how they handle the TR on
Hi all,
I've hit a blocker on getting this working for AMD's SVM and would
appreciate any thoughts. Hopefully I've missed a much simpler way of
doing this or I've missed something!
So, AMD and Intel differ in how they handle the TR on a VMEXIT and
VMRUM. On a VMEXIT, Intel Save the guest's T
