Hello,
On 05/03/2015 09:31, Frediano Ziglio wrote:
But some offsets are different... so I'd like a confirmation based on
some spec.
You can find spec at https://github.com/hisilicon/boards/tree/master/D01/docs.
The spec is in Chinese... Any chance to have an English version?
Regards,
--
J
2015-03-03 15:42 GMT+00:00 Julien Grall :
> On 03/03/15 15:36, Frediano Ziglio wrote:
>>>
>>> Hello Frediano,
>>>
>>> On 03/03/15 11:19, Frediano Ziglio wrote:
The GIC in this platform is mainly compatible with the standard
GICv2 beside:
- ITARGET is extended to 16 bit to support 16
On 03/03/15 15:36, Frediano Ziglio wrote:
>>
>> Hello Frediano,
>>
>> On 03/03/15 11:19, Frediano Ziglio wrote:
>>> The GIC in this platform is mainly compatible with the standard
>>> GICv2 beside:
>>> - ITARGET is extended to 16 bit to support 16 CPUs;
>>> - SGI mask is extended to support 16 CPUs
>
> Hello Frediano,
>
> On 03/03/15 11:19, Frediano Ziglio wrote:
> > The GIC in this platform is mainly compatible with the standard
> > GICv2 beside:
> > - ITARGET is extended to 16 bit to support 16 CPUs;
> > - SGI mask is extended to support 16 CPUs;
> > - maximum supported interrupt is 510;
Hello Frediano,
On 03/03/15 11:19, Frediano Ziglio wrote:
> The GIC in this platform is mainly compatible with the standard
> GICv2 beside:
> - ITARGET is extended to 16 bit to support 16 CPUs;
> - SGI mask is extended to support 16 CPUs;
> - maximum supported interrupt is 510;
510 is not a multi
The GIC in this platform is mainly compatible with the standard
GICv2 beside:
- ITARGET is extended to 16 bit to support 16 CPUs;
- SGI mask is extended to support 16 CPUs;
- maximum supported interrupt is 510;
- GICH APR and LR register offsets.
Signed-off-by: Frediano Ziglio
Signed-off-by: Zolt
