On 13/04/15 11:51, Jan Beulich wrote:
On 27.03.15 at 19:31, wrote:
>> On 26/03/15 12:38, Chao Peng wrote:
>>> +cpuid_count(PSR_CPUID_LEVEL_CAT, 0, &eax, &ebx, &ecx, &edx);
>>> +if ( ebx & PSR_RESOURCE_TYPE_L3 )
>>> +{
>>> +cpuid_count(PSR_CPUID_LEVEL_CAT, 1, &eax, &ebx, &e
>>> On 27.03.15 at 19:31, wrote:
> On 26/03/15 12:38, Chao Peng wrote:
>> +cpuid_count(PSR_CPUID_LEVEL_CAT, 0, &eax, &ebx, &ecx, &edx);
>> +if ( ebx & PSR_RESOURCE_TYPE_L3 )
>> +{
>> +cpuid_count(PSR_CPUID_LEVEL_CAT, 1, &eax, &ebx, &ecx, &edx);
>> +info->cbm_len = (eax
On 26/03/15 12:38, Chao Peng wrote:
> Detect Intel Cache Allocation Technology(CAT) feature and store the
> cpuid information for later use. Currently only L3 cache allocation is
> supported. The L3 CAT features may vary among sockets so per-socket
> feature information is stored. The initializatio
Detect Intel Cache Allocation Technology(CAT) feature and store the
cpuid information for later use. Currently only L3 cache allocation is
supported. The L3 CAT features may vary among sockets so per-socket
feature information is stored. The initialization can happen either at
boot time or when CPU
