Re: [Xen-devel] [PATCH v3 3/3] x86/vmx: fix vmentry failure with TSX bits in LBR

2017-02-26 Thread Tian, Kevin
> From: Sergey Dyasli [mailto:sergey.dya...@citrix.com] > Sent: Thursday, February 23, 2017 5:33 PM > > During VM entry, H/W will automatically load guest's MSRs from MSR-load > area in the same way as they would be written by WRMSR. > > However, under the following conditions: > > 1. LBR (L

Re: [Xen-devel] [PATCH v3 3/3] x86/vmx: fix vmentry failure with TSX bits in LBR

2017-02-23 Thread Jan Beulich
>>> On 23.02.17 at 10:33, wrote: > During VM entry, H/W will automatically load guest's MSRs from MSR-load > area in the same way as they would be written by WRMSR. > > However, under the following conditions: > > 1. LBR (Last Branch Record) MSRs were placed in the MSR-load area > 2. Add

[Xen-devel] [PATCH v3 3/3] x86/vmx: fix vmentry failure with TSX bits in LBR

2017-02-23 Thread Sergey Dyasli
During VM entry, H/W will automatically load guest's MSRs from MSR-load area in the same way as they would be written by WRMSR. However, under the following conditions: 1. LBR (Last Branch Record) MSRs were placed in the MSR-load area 2. Address format of LBR includes TSX bits 61:62 3