>>> On 22.02.17 at 14:58, wrote:
> On Wed, 2017-02-22 at 03:26 -0700, Jan Beulich wrote:
>> > > > On 17.02.17 at 16:42, wrote:
>> > --- a/xen/include/asm-x86/msr-index.h
>> > +++ b/xen/include/asm-x86/msr-index.h
>> > @@ -55,6 +55,8 @@
>> > #define MSR_IA32_PEBS_ENABLE 0x03f1
>>
On 22/02/17 13:58, Sergey Dyasli wrote:
>
>>> @@ -2876,7 +2938,11 @@ static int vmx_msr_write_intercept(unsigned int msr,
>>> uint64_t msr_content)
>>> for ( ; (rc == 0) && lbr->count; lbr++ )
>>> for ( i = 0; (rc == 0) && (i < lbr->count); i++ )
>>>
On Wed, 2017-02-22 at 03:26 -0700, Jan Beulich wrote:
> > > > On 17.02.17 at 16:42, wrote:
> >
> > --- a/xen/arch/x86/hvm/vmx/vmx.c
> > +++ b/xen/arch/x86/hvm/vmx/vmx.c
> > @@ -2284,6 +2284,8 @@ static void pi_notification_interrupt(struct
> > cpu_user_regs *regs)
> > raise_softirq(VCPU_KIC
>>> On 17.02.17 at 16:42, wrote:
> --- a/xen/arch/x86/hvm/vmx/vmx.c
> +++ b/xen/arch/x86/hvm/vmx/vmx.c
> @@ -2284,6 +2284,8 @@ static void pi_notification_interrupt(struct
> cpu_user_regs *regs)
> raise_softirq(VCPU_KICK_SOFTIRQ);
> }
>
> +static void __init vmx_lbr_tsx_fixup_check(void);
> From: Andrew Cooper [mailto:andrew.coop...@citrix.com]
> Sent: Tuesday, February 21, 2017 7:25 PM
>
> On 21/02/17 09:13, Tian, Kevin wrote:
> >> @@ -2618,6 +2630,56 @@ static const struct lbr_info
> >> *last_branch_msr_get(void)
> >> return NULL;
> >> }
> >>
> >> +enum
> >> +{
> >> +L
On 21/02/17 09:13, Tian, Kevin wrote:
>> @@ -2618,6 +2630,56 @@ static const struct lbr_info
>> *last_branch_msr_get(void)
>> return NULL;
>> }
>>
>> +enum
>> +{
>> +LBR_FORMAT_32 = 0x0, /* 32-bit record format */
>> +LBR_FORMAT_LIP= 0x1, /* 64-bit LIP
> From: Sergey Dyasli [mailto:sergey.dya...@citrix.com]
> Sent: Friday, February 17, 2017 11:43 PM
>
> During VM entry, H/W will automatically load guest's MSRs from MSR-load
> area in the same way as they would be written by WRMSR.
>
> However, under the following conditions:
>
> 1. LBR (La
During VM entry, H/W will automatically load guest's MSRs from MSR-load
area in the same way as they would be written by WRMSR.
However, under the following conditions:
1. LBR (Last Branch Record) MSRs were placed in the MSR-load area
2. Address format of LBR includes TSX bits 61:62
3
