Re: [Xen-devel] [PATCH v2 1/4] arm: processor: rename iss to res0 in hsr_cond union

2017-08-09 Thread Julien Grall
Hi Volodymyr, On 09/08/2017 20:44, Volodymyr Babchuk wrote: Name "iss" in this case was used not exactly correctly, because this is only part of HSR.ISS field. ARM refence manual denotes this part of ISS as RES0 when it describes encoding for conditional exceptions (ARM DDI 0487A.k pages D7-1939

[Xen-devel] [PATCH v2 1/4] arm: processor: rename iss to res0 in hsr_cond union

2017-08-09 Thread Volodymyr Babchuk
Name "iss" in this case was used not exactly correctly, because this is only part of HSR.ISS field. ARM refence manual denotes this part of ISS as RES0 when it describes encoding for conditional exceptions (ARM DDI 0487A.k pages D7-1939 - D7-1949). Signed-off-by: Volodymyr Babchuk --- - Added re