On 17/02/15 17:38, Boris Ostrovsky wrote:
> On 02/17/2015 10:13 AM, Andrew Cooper wrote:
>> On 16/02/15 22:26, Boris Ostrovsky wrote:
>>> Changes in v18:
>>>
>>> * Return 1 (i.e. "handled") in vpmu_do_interrupt() if PMU_CACHED is
>>>set. This is needed since we can get an interrupt while this f
On 02/17/2015 10:13 AM, Andrew Cooper wrote:
On 16/02/15 22:26, Boris Ostrovsky wrote:
Changes in v18:
* Return 1 (i.e. "handled") in vpmu_do_interrupt() if PMU_CACHED is
set. This is needed since we can get an interrupt while this flag is
set on AMD processors when multiple counters are
On 16/02/15 22:26, Boris Ostrovsky wrote:
> Changes in v18:
>
> * Return 1 (i.e. "handled") in vpmu_do_interrupt() if PMU_CACHED is
> set. This is needed since we can get an interrupt while this flag is
> set on AMD processors when multiple counters are in use (**) (AMD
> processor don't mask
Changes in v18:
* Return 1 (i.e. "handled") in vpmu_do_interrupt() if PMU_CACHED is
set. This is needed since we can get an interrupt while this flag is
set on AMD processors when multiple counters are in use (**) (AMD
processor don't mask LVTPC when PMC interrupt happens and so there
is a
