On 11/16/2014 02:08 PM, Ingo Molnar wrote:
* Juergen Gross wrote:
arch/x86/include/asm/cacheflush.h | 38 ---
FYI, this series breaks the UML build:
In file included from /home/mingo/tip/include/linux/highmem.h:11:0,
from /home/mingo/tip/include/linux/pagema
* Juergen Gross wrote:
> arch/x86/include/asm/cacheflush.h | 38 ---
FYI, this series breaks the UML build:
In file included from /home/mingo/tip/include/linux/highmem.h:11:0,
from /home/mingo/tip/include/linux/pagemap.h:10,
from /home/mingo/tip/i
Ingo,
could you take the patches, please?
Juergen
On 11/03/2014 02:01 PM, Juergen Gross wrote:
The x86 architecture offers via the PAT (Page Attribute Table) a way to
specify different caching modes in page table entries. The PAT MSR contains
8 entries each specifying one of 6 possible cache
