On Tue, 2015-12-15 at 11:41 +, Julien Grall wrote:
> Hi Ian,
Thanks for the replies, I think mostly adding the further exposition from
this thread to the commit message would make this patch OK.
>
> On 15/12/15 11:10, Ian Campbell wrote:
> > On Fri, 2015-12-11 at 15:28 +, Julien Grall wro
Hi Ian,
On 15/12/15 11:10, Ian Campbell wrote:
> On Fri, 2015-12-11 at 15:28 +, Julien Grall wrote:
>> On AArch64, the encoding 31 could be used to represent {x,w}sp or
>> {x,w}zr (See C1.2.4 in ARM DDI 0486A.d). The choice will depend how the
>> register field is interpreted by the instructio
On Fri, 2015-12-11 at 15:28 +, Julien Grall wrote:
> On AArch64, the encoding 31 could be used to represent {x,w}sp or
> {x,w}zr (See C1.2.4 in ARM DDI 0486A.d). The choice will depend how the
> register field is interpreted by the instruction.
>
> All the instructions trapped by Xen (either v
On AArch64, the encoding 31 could be used to represent {x,w}sp or
{x,w}zr (See C1.2.4 in ARM DDI 0486A.d). The choice will depend how the
register field is interpreted by the instruction.
All the instructions trapped by Xen (either via a sysreg access or data
abort) interprets the encoding 31 as z
