On 07/28/2017 09:31 PM, Julien Grall wrote:
Hi,
On 07/28/2017 08:43 PM, Volodymyr Babchuk wrote:
On ARMv8, one of conditional exceptions (SMC that originates
from aarch32 state) have extra field in HCR.ISS encoding:
CCKNOWNPASS, bit [19]
Indicates whether the instruction might have failed it
Hi,
On 07/28/2017 08:43 PM, Volodymyr Babchuk wrote:
On ARMv8, one of conditional exceptions (SMC that originates
from aarch32 state) have extra field in HCR.ISS encoding:
CCKNOWNPASS, bit [19]
Indicates whether the instruction might have failed its condition
code check.
0 - The instruction
On ARMv8, one of conditional exceptions (SMC that originates
from aarch32 state) have extra field in HCR.ISS encoding:
CCKNOWNPASS, bit [19]
Indicates whether the instruction might have failed its condition
code check.
0 - The instruction was unconditional, or was conditional and
passed its
