>>> On 03.12.15 at 09:38, wrote:
> btw are you still requiring Intel review for whole this patch set? still
> looking at 4/4 now...
Iirc the whole series went in meanwhile. I.e. I wouldn't call it
"require", but "nice to have" (ensuring you don't spot an issue
with what already got committed).
J
> From: Jan Beulich [mailto:jbeul...@suse.com]
> Sent: Thursday, December 03, 2015 4:15 PM
>
> >>> On 03.12.15 at 08:46, wrote:
> >> From: Jan Beulich
> >> Sent: Wednesday, November 11, 2015 1:38 AM
> >>
> >> Signed-off-by: Jan Beulich
> >
> > A simple description why error code is not required
>>> On 03.12.15 at 08:46, wrote:
>> From: Jan Beulich
>> Sent: Wednesday, November 11, 2015 1:38 AM
>>
>> Signed-off-by: Jan Beulich
>
> A simple description why error code is not required is preferred here.
Well, anyone knowing what #DB means should also know that an
error code is not only n
> From: Jan Beulich
> Sent: Wednesday, November 11, 2015 1:38 AM
>
> Signed-off-by: Jan Beulich
A simple description why error code is not required is preferred here.
>
> --- a/xen/arch/x86/hvm/hvm.c
> +++ b/xen/arch/x86/hvm/hvm.c
> @@ -4133,7 +4133,7 @@ void hvm_task_switch(
> goto o
On 10/11/15 17:38, Jan Beulich wrote:
> Signed-off-by: Jan Beulich
Reviewed-by: Andrew Cooper
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Signed-off-by: Jan Beulich
--- a/xen/arch/x86/hvm/hvm.c
+++ b/xen/arch/x86/hvm/hvm.c
@@ -4133,7 +4133,7 @@ void hvm_task_switch(
goto out;
if ( (tss.trace & 1) && !exn_raised )
-hvm_inject_hw_exception(TRAP_debug, tss_sel & 0xfff8);
+hvm_inject_hw_exception(TRAP_de
