On 27/02/17 11:34, Andre Przywara wrote:
Hi,
Hi Andre,
"Yes, will fix" to everything not explicitly mentioned below.
On 06/02/17 16:26, Julien Grall wrote:
Hi Andre,
On 30/01/17 18:31, Andre Przywara wrote:
The ARM GICv3 provides a new kind of interrupt called LPIs.
The pending bits an
Hi,
"Yes, will fix" to everything not explicitly mentioned below.
On 06/02/17 16:26, Julien Grall wrote:
> Hi Andre,
>
> On 30/01/17 18:31, Andre Przywara wrote:
>> The ARM GICv3 provides a new kind of interrupt called LPIs.
>> The pending bits and the configuration data (priority, enable bits)
On Mon, 30 Jan 2017, Andre Przywara wrote:
> The ARM GICv3 provides a new kind of interrupt called LPIs.
> The pending bits and the configuration data (priority, enable bits) for
> those LPIs are stored in tables in normal memory, which software has to
> provide to the hardware.
> Allocate the requ
Hi Andre,
On 30/01/17 18:31, Andre Przywara wrote:
The ARM GICv3 provides a new kind of interrupt called LPIs.
The pending bits and the configuration data (priority, enable bits) for
those LPIs are stored in tables in normal memory, which software has to
provide to the hardware.
Allocate the req
The ARM GICv3 provides a new kind of interrupt called LPIs.
The pending bits and the configuration data (priority, enable bits) for
those LPIs are stored in tables in normal memory, which software has to
provide to the hardware.
Allocate the required memory, initialize it and hand it over to each
r
