>>> On 12.01.17 at 17:43, wrote:
> On 12/01/17 16:12, Jan Beulich wrote:
> On 12.01.17 at 16:04, wrote:
>>> On 12/01/17 14:02, Jan Beulich wrote:
Furthermore I think we have another issue with writes: If the write
faults, the FSW (or MXCSR, albeit there only for instructions we don'
>>> On 12.01.17 at 17:43, wrote:
> On 12/01/17 16:12, Jan Beulich wrote:
> On 12.01.17 at 16:04, wrote:
>>> On 12/01/17 14:02, Jan Beulich wrote:
Furthermore I think we have another issue with writes: If the write
faults, the FSW (or MXCSR, albeit there only for instructions we don'
On 12/01/17 16:12, Jan Beulich wrote:
On 12.01.17 at 16:04, wrote:
>> On 12/01/17 14:02, Jan Beulich wrote:
>>> Furthermore I think we have another issue with writes: If the write
>>> faults, the FSW (or MXCSR, albeit there only for instructions we don't
>>> emulate yet) register may have bee
>>> On 12.01.17 at 16:04, wrote:
> On 12/01/17 14:02, Jan Beulich wrote:
>> Furthermore I think we have another issue with writes: If the write
>> faults, the FSW (or MXCSR, albeit there only for instructions we don't
>> emulate yet) register may have been updated already, so we'd need to
>> undo
On 12/01/17 14:02, Jan Beulich wrote:
> FPU insns writing to memory must not touch memory if they latch #MF (to
> be delivered on the next waiting FPU insn). Note that inspecting FSW.ES
> needs to be avoided for all FNST* insns, as they don't raise exceptions
> themselves, but may instead be invoke
FPU insns writing to memory must not touch memory if they latch #MF (to
be delivered on the next waiting FPU insn). Note that inspecting FSW.ES
needs to be avoided for all FNST* insns, as they don't raise exceptions
themselves, but may instead be invoked with the bit already set.
Signed-off-by: Ja
