On 04/24/2017 12:00 PM, Boris Ostrovsky wrote:
Also, from the description in the SDM, PC flag bit it seems very
disruptive to me.
SDM says that if the bit is set then the processor toggles the PMi pin
(generating a performance monitoring interrupt?)
every time the event occurs. So if we program
>>> On 24.04.17 at 17:44, wrote:
> On 04/21/2017 03:14 AM, Jan Beulich wrote:
> On 20.04.17 at 19:49, wrote:
>>> This patch changes wrmsrl() calls to write to MSR_P6_EVTSEL register in the
>>> VPMU to wrmsr_safe(). There are known (and possibly some unknown) cases
>>> where
>>> setting certa
>
> Also, from the description in the SDM, PC flag bit it seems very
> disruptive to me.
> SDM says that if the bit is set then the processor toggles the PMi pin
> (generating a performance monitoring interrupt?)
> every time the event occurs. So if we program the counter to count
> "unhaulted cor
On 04/21/2017 03:14 AM, Jan Beulich wrote:
On 20.04.17 at 19:49, wrote:
This patch changes wrmsrl() calls to write to MSR_P6_EVTSEL register in the
VPMU to wrmsr_safe(). There are known (and possibly some unknown) cases where
setting certain bits in MSR_P6_EVTSEL reg. can cause a General Prot
>>> On 20.04.17 at 19:49, wrote:
> This patch changes wrmsrl() calls to write to MSR_P6_EVTSEL register in the
> VPMU to wrmsr_safe(). There are known (and possibly some unknown) cases where
> setting certain bits in MSR_P6_EVTSEL reg. can cause a General Protection
> fault on some machines. Unles
This patch changes wrmsrl() calls to write to MSR_P6_EVTSEL register in the
VPMU to wrmsr_safe(). There are known (and possibly some unknown) cases where
setting certain bits in MSR_P6_EVTSEL reg. can cause a General Protection
fault on some machines. Unless we catch this fault when it happens, it
