Adding personal email id for future correspondence on this thread -
mgamb...@outlook.com
On 05/04/2017 05:13 PM, Mohit Gambhir wrote:
On 05/03/2017 04:41 PM, Andrew Cooper wrote:
On 25/04/17 22:45, Mohit Gambhir wrote:
diff --git a/tests/vpmu/Makefile b/tests/vpmu/Makefile
new file mode
.
Mohit Gambhir (2):
xtf/vpmu: Add Intel PMU MSR addresses
xtf/vpmu: MSR read/write tests for VPMU
arch/x86/include/arch/msr-index.h | 12 ++
tests/vpmu/Makefile | 9 +
tests/vpmu/main.c | 442 ++
3 files changed, 463 insertions
This patch adds Intel PMU MSR addresses as macros for VPMU testing
Signed-off-by: Mohit Gambhir
---
arch/x86/include/arch/msr-index.h | 12
1 file changed, 12 insertions(+)
diff --git a/arch/x86/include/arch/msr-index.h
b/arch/x86/include/arch/msr-index.h
index 72373c6..911d7f9
currently unsupported for AMD machines and PV guests.
Signed-off-by: Mohit Gambhir
---
tests/vpmu/Makefile | 9 ++
tests/vpmu/main.c | 442
2 files changed, 451 insertions(+)
create mode 100644 tests/vpmu/Makefile
create mode 100644 tests/vpmu
, the PC flag bit toggles a hardware pin on the physical CPU
every time the programmed event occurs and the hardware behavior in
response to the toggle is undefined in the SDM, which makes this bit
unsafe to be used by guests and hence should be masked on all machines.
Signed-off-by: Mohit Ga
On 05/03/2017 04:41 PM, Andrew Cooper wrote:
On 25/04/17 22:45, Mohit Gambhir wrote:
diff --git a/tests/vpmu/Makefile b/tests/vpmu/Makefile
new file mode 100644
index 000..1eaf436
--- /dev/null
+++ b/tests/vpmu/Makefile
@@ -0,0 +1,9 @@
+include $(ROOT)/build/common.mk
+
+NAME := vpmu
AM, Jan Beulich wrote:
On 26.04.17 at 20:50, wrote:
On 04/26/2017 02:19 PM, Andrew Cooper wrote:
On 26/04/17 19:11, Mohit Gambhir wrote:
Setting Pin Control (PC) bit (19) in MSR_P6_EVNTSEL results in a
General
Protection Fault and thus results in a hypervisor crash. This patch
fixes
the
On 04/25/2017 02:50 PM, Andrew Cooper wrote:
On 24/04/17 18:54, Mohit Gambhir wrote:
Mohit Gambhir (2):
xtf/vpmu: Add Intel PMU MSR addresses
xtf/vpmu: MSR read/write tests for VPMU
arch/x86/include/arch/msr-index.h | 11 +
tests/vpmu/Makefile | 9 +
tests/vpmu
This patch adds Intel PMU MSR addresses as macros for VPMU testing
Signed-off-by: Mohit Gambhir
---
arch/x86/include/arch/msr-index.h | 12
1 file changed, 12 insertions(+)
diff --git a/arch/x86/include/arch/msr-index.h
b/arch/x86/include/arch/msr-index.h
index 72373c6..911d7f9
currently unsupported for AMD machines and PV guests.
Signed-off-by: Mohit Gambhir
---
tests/vpmu/Makefile | 9 ++
tests/vpmu/main.c | 442
2 files changed, 451 insertions(+)
create mode 100644 tests/vpmu/Makefile
create mode 100644 tests/vpmu
exposed incorrectly.
Mohit Gambhir (2):
xtf/vpmu: Add Intel PMU MSR addresses
xtf/vpmu: MSR read/write tests for VPMU
arch/x86/include/arch/msr-index.h | 12 ++
tests/vpmu/Makefile | 9 +
tests/vpmu/main.c | 433 ++
3 files
On 04/26/2017 02:19 PM, Andrew Cooper wrote:
On 26/04/17 19:11, Mohit Gambhir wrote:
Setting Pin Control (PC) bit (19) in MSR_P6_EVNTSEL results in a General
Protection Fault and thus results in a hypervisor crash. This patch fixes the
crash by masking PC bit and returning an error in case
Setting Pin Control (PC) bit (19) in MSR_P6_EVNTSEL results in a General
Protection Fault and thus results in a hypervisor crash. This patch fixes the
crash by masking PC bit and returning an error in case any guest tries to write
to it.
Signed-off-by: Mohit Gambhir
---
v2 of this patch takes a
On 04/25/2017 02:20 PM, Andrew Cooper wrote:
On 24/04/17 18:54, Mohit Gambhir wrote:
This patch tests VPMU functionality in the hypervisor on Intel machines.
The tests write to all valid bits in the MSRs that get exposed to the guests
when VPMU is enabled. The tests also write invalid values
On 04/25/2017 11:24 AM, Andrew Cooper wrote:
On 24/04/17 18:54, Mohit Gambhir wrote:
This patch adds Intel PMU MSR addresses as macros for VPMU testing
Signed-off-by: Mohit Gambhir
---
arch/x86/include/arch/msr-index.h | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch
On 04/25/2017 04:36 AM, Jan Beulich wrote:
On 24.04.17 at 19:54, wrote:
--- a/arch/x86/include/arch/msr-index.h
+++ b/arch/x86/include/arch/msr-index.h
@@ -38,6 +38,17 @@
#define MSR_GS_BASE 0xc101
#define MSR_SHADOW_GS_BASE 0xc102
+#define MSR_
On 04/24/2017 12:00 PM, Boris Ostrovsky wrote:
Also, from the description in the SDM, PC flag bit it seems very
disruptive to me.
SDM says that if the bit is set then the processor toggles the PMi pin
(generating a performance monitoring interrupt?)
every time the event occurs. So if we program
currently unsupported for AMD machines and PV guests.
Signed-off-by: Mohit Gambhir
---
tests/vpmu/Makefile | 9 +
tests/vpmu/main.c | 504
2 files changed, 513 insertions(+)
create mode 100644 tests/vpmu/Makefile
create mode 100644 tests/vpmu
.
Further testing is required to validate the MSR state save/restore functionality
of the VPMU, concurrent usage of the counters by a number of guests and analyze
if any other non-PMU MSRs have been exposed incorrectly
Mohit Gambhir (2):
xtf
This patch adds Intel PMU MSR addresses as macros for VPMU testing
Signed-off-by: Mohit Gambhir
---
arch/x86/include/arch/msr-index.h | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/x86/include/arch/msr-index.h
b/arch/x86/include/arch/msr-index.h
index 2e90079..3a79025
On 04/24/2017 01:46 PM, Mohit Gambhir wrote:
This patch adds Intel PMU MSR addresses as macros for VPMU testing
Signed-off-by: Mohit Gambhir
---
arch/x86/include/arch/msr-index.h | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/x86/include/arch/msr-index.h
b/arch/x86
This patch adds Intel PMU MSR addresses as macros for VPMU testing
Signed-off-by: Mohit Gambhir
---
arch/x86/include/arch/msr-index.h | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/x86/include/arch/msr-index.h
b/arch/x86/include/arch/msr-index.h
index 2e90079..3a79025
.
Further testing is required to validate the MSR state save/restore functionality
of the VPMU, concurrent usage of the counters by a number of guests and analyze
if any other non-PMU MSRs have been exposed incorrectly
Mohit Gambhir (2):
xtf
currently unsupported for AMD machines and PV guests.
Signed-off-by: Mohit Gambhir
---
tests/vpmu/Makefile | 9 +
tests/vpmu/main.c | 504
2 files changed, 513 insertions(+)
create mode 100644 tests/vpmu/Makefile
create mode 100644 tests/vpmu
On 04/21/2017 05:43 AM, Wei Liu wrote:
On Thu, Apr 20, 2017 at 04:40:08PM -0400, Mohit Gambhir wrote:
This patch tests VPMU functionality in the hypervisor on Intel machines.
The tests write to all valid bits in the MSRs that get exposed to the guests
when VPMU is enabled. The tests also
On 04/21/2017 02:31 AM, Jan Beulich wrote:
On 20.04.17 at 22:40, wrote:
--- a/arch/x86/include/arch/msr-index.h
+++ b/arch/x86/include/arch/msr-index.h
@@ -38,6 +38,17 @@
#define MSR_GS_BASE 0xc101
#define MSR_SHADOW_GS_BASE 0xc102
+#define MSR_
On 04/21/2017 03:14 AM, Jan Beulich wrote:
On 20.04.17 at 19:49, wrote:
This patch changes wrmsrl() calls to write to MSR_P6_EVTSEL register in the
VPMU to wrmsr_safe(). There are known (and possibly some unknown) cases where
setting certain bits in MSR_P6_EVTSEL reg. can cause a General Prot
This patch adds Intel PMU MSR addresses as macros for VPMU testing
Signed-off-by: Mohit Gambhir
---
arch/x86/include/arch/msr-index.h | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/x86/include/arch/msr-index.h
b/arch/x86/include/arch/msr-index.h
index 2e90079..7df9097
currently unsupported for AMD machines and PV guests.
Signed-off-by: Mohit Gambhir
---
tests/vpmu/Makefile | 9 +
tests/vpmu/main.c | 502
2 files changed, 511 insertions(+)
create mode 100644 tests/vpmu/Makefile
create mode 100644 tests/vpmu
with reasonable
caveats.
Further testing is required to validate the MSR state save/restore functionality
of the VPMU, concurrent usage of the counters by a number of guests and analyze
if any other non-PMU MSRs have been exposed incorrectly.
Mohit Gambhir (2):
xtf/vpmu: Add Intel PMU MSR
allow any writes to it from guests
on any Intel machine.
2. Use wrmsr_safe() function to write to IA32_PERF_EVTSELx register and return
any resulting fault to the guest OS.
The attached patch uses solution 2 so as to not disable PC flag bit on machines
that do not fault.
Mohit Gambhir (1):
x86
occur while writing MSR_P6_EVNTSEL reg) by
catching and returning the fault to the guest OS.
Signed-off-by: Mohit Gambhir
---
xen/arch/x86/cpu/vpmu_intel.c | 20 +---
1 file changed, 13 insertions(+), 7 deletions(-)
diff --git a/xen/arch/x86/cpu/vpmu_intel.c b/xen/arch/x86/cpu
olution).
Signed-off-by: Mohit Gambhir
---
xen/arch/x86/cpu/vpmu_intel.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/xen/arch/x86/cpu/vpmu_intel.c b/xen/arch/x86/cpu/vpmu_intel.c
index 0d66ecb..3f0322c 100644
--- a/xen/arch/x86/cpu/vpmu_intel.c
+++ b/xen/arch/x86
On 04/03/2017 06:36 AM, Jan Beulich wrote:
On 31.03.17 at 16:46, wrote:
This patch masks .AnyThread bits in IA32_FIXED_CTR_CTRL MSR for all
versions of Intel Arhcitectural Performance Monitoring. Note that
.AnyThread bit (21) is already masked in IA32_PERFEVTSELx MSRs since
hyperthreading is
virtualized environments (per section 18.2.3.1
AnyThread Counting and Software Evolution)
Signed-off-by: Mohit Gambhir
---
xen/arch/x86/cpu/vpmu_intel.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/xen/arch/x86/cpu/vpmu_intel.c b/xen/arch/x86/cpu/vpmu_intel.c
index
instead of
calling xen_apic_read().
The warning is not seen on AMD machines because init_amd() populates
cpu_data(cpu).apicid by calling hard_smp_processor_id()->xen_apic_read()
as opposed to using apicid from cpuid as is done on Intel machines.
Signed-off-by: Mohit Gambhir
---
arch/x86/xen/
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