Hi Wei,
Thanks for your comments. Please see my reply below.
On 7/29/2017 1:40 AM, Wei Liu wrote:
On Tue, Jul 18, 2017 at 08:22:55PM +1200, Huang, Kai wrote:
Hi Wei,
Thank you very much for comments. Please see my reply below.
On 7/17/2017 9:16 PM, Wei Liu wrote:
Hi Kai
Thanks for this
On 7/21/2017 9:42 PM, Huang, Kai wrote:
On 7/20/2017 5:27 AM, Andrew Cooper wrote:
On 09/07/17 09:09, Kai Huang wrote:
This patch handles IA32_FEATURE_CONTROL and IA32_SGXLEPUBKEYHASHn MSRs.
For IA32_FEATURE_CONTROL, if SGX is exposed to domain, then
SGX_ENABLE bit
is always set. If SGX
On 7/21/2017 9:17 PM, Huang, Kai wrote:
On 7/20/2017 2:23 AM, Andrew Cooper wrote:
On 09/07/17 09:09, Kai Huang wrote:
This patch adds early stage SGX feature detection via SGX CPUID 0x12.
Function
detect_sgx is added to detect SGX info on each CPU (called from
vmx_cpu_up).
SDM says SGX
On 7/20/2017 5:27 AM, Andrew Cooper wrote:
On 09/07/17 09:09, Kai Huang wrote:
This patch handles IA32_FEATURE_CONTROL and IA32_SGXLEPUBKEYHASHn MSRs.
For IA32_FEATURE_CONTROL, if SGX is exposed to domain, then SGX_ENABLE bit
is always set. If SGX launch control is also exposed to domain, and
On 7/20/2017 2:23 AM, Andrew Cooper wrote:
On 09/07/17 09:09, Kai Huang wrote:
This patch adds early stage SGX feature detection via SGX CPUID 0x12. Function
detect_sgx is added to detect SGX info on each CPU (called from vmx_cpu_up).
SDM says SGX info returned by CPUID is per-thread, and we c
On 7/17/2017 6:08 PM, Huang, Kai wrote:
Hi Andrew,
Thank you very much for comments. Sorry for late reply, and please see
my reply below.
On 7/12/2017 2:13 AM, Andrew Cooper wrote:
On 09/07/17 09:03, Kai Huang wrote:
Hi all,
This series is RFC Xen SGX virtualization support design and
On 7/18/2017 10:21 PM, Roger Pau Monné wrote:
On Tue, Jul 18, 2017 at 08:36:15PM +1200, Huang, Kai wrote:
On 7/17/2017 10:54 PM, Roger Pau Monné wrote:
On Sun, Jul 09, 2017 at 08:16:05PM +1200, Kai Huang wrote:
On physical machine EPC is exposed in ACPI table via "INT0E0C". Al
On 7/18/2017 10:12 PM, Andrew Cooper wrote:
On 09/07/17 09:04, Kai Huang wrote:
Expose SGX in CPU featureset for HVM domain. SGX will not be supported for
PV domain, as ENCLS (which SGX driver in guest essentially runs) must run
in ring 0, while PV kernel runs in ring 3. Theoretically we can s
On 7/17/2017 10:54 PM, Roger Pau Monné wrote:
On Sun, Jul 09, 2017 at 08:16:05PM +1200, Kai Huang wrote:
On physical machine EPC is exposed in ACPI table via "INT0E0C". Although EPC
can be discovered by CPUID but Windows driver requires EPC to be exposed in
ACPI table as well. This patch expos
Hi Wei,
Thank you very much for comments. Please see my reply below.
On 7/17/2017 9:16 PM, Wei Liu wrote:
Hi Kai
Thanks for this nice write-up.
Some comments and questions below.
On Sun, Jul 09, 2017 at 08:03:10PM +1200, Kai Huang wrote:
Hi all,
[...]
2. SGX Virtualization Design
2.1 Hi
On 7/12/2017 11:09 PM, Andrew Cooper wrote:
On 09/07/17 10:04, Kai Huang wrote:
Expose SGX in CPU featureset for HVM domain. SGX will not be supported
for
PV domain, as ENCLS (which SGX driver in guest essentially runs) must run
in ring 0, while PV kernel runs in ring 3. Theoretically we can
On 7/14/2017 7:37 PM, Andrew Cooper wrote:
On 13/07/17 07:42, Huang, Kai wrote:
On 7/12/2017 10:56 PM, Andrew Cooper wrote:
On 09/07/17 10:10, Kai Huang wrote:
Why do we need this hide_epc parameter? If we aren't providing any
epc resource to the guest, the entire sgx union should be
On 7/14/2017 11:31 PM, Jan Beulich wrote:
On 09.07.17 at 10:16, wrote:
--- a/tools/firmware/hvmloader/util.c
+++ b/tools/firmware/hvmloader/util.c
@@ -330,6 +330,15 @@ cpuid(uint32_t idx, uint32_t *eax, uint32_t *ebx, uint32_t
*ecx, uint32_t *edx)
: "0" (idx) );
}
+void cpuid_
Hi Andrew,
Thank you very much for comments. Sorry for late reply, and please see
my reply below.
On 7/12/2017 2:13 AM, Andrew Cooper wrote:
On 09/07/17 09:03, Kai Huang wrote:
Hi all,
This series is RFC Xen SGX virtualization support design and RFC draft
patches.
Thankyou very much for
On 7/12/2017 11:05 PM, Andrew Cooper wrote:
On 09/07/17 10:16, Kai Huang wrote:
On physical machine EPC is exposed in ACPI table via "INT0E0C".
Although EPC
can be discovered by CPUID but Windows driver requires EPC to be
exposed in
ACPI table as well. This patch exposes EPC in ACPI table.
On 7/13/2017 12:21 AM, George Dunlap wrote:
On Jul 12, 2017, at 1:01 PM, Andrew Cooper wrote:
On 09/07/17 10:12, Kai Huang wrote:
A new 'p2m_epc' type is added for EPC mapping type. Two wrapper functions
set_epc_p2m_entry and clear_epc_p2m_entry are also added for further use.
Other grou
On 7/12/2017 10:56 PM, Andrew Cooper wrote:
On 09/07/17 10:10, Kai Huang wrote:
This patch adds SGX to cpuid handling support. In init_guest_cpuid, for
raw_policy and host_policy, physical EPC info is reported, but for
pv_max_policy
and hvm_max_policy EPC is hidden, as for particular domain,
On 7/12/2017 7:13 PM, Julien Grall wrote:
On 07/12/2017 02:52 AM, Huang, Kai wrote:
Hi Julien,
Hello Kai,
Please avoid top-posting.
Sorry. Will avoid in the future :)
Thanks for pointing out. I'll move to x86 specific.
I've cc-ed all maintainers reported by
On 7/12/2017 6:17 PM, Jan Beulich wrote:
Julien Grall 07/11/17 10:15 PM >>>
On 07/09/2017 09:10 AM, Kai Huang wrote:
Currently Xen only has non-cacheable version of ioremap. Although EPC is
reported as reserved memory in e820 but it can be mapped as cacheable. This
patch adds ioremap_cache (
On 7/13/2017 6:54 AM, Jan Beulich wrote:
Andrew Cooper 07/12/17 1:12 PM >>>
On 09/07/17 10:09, Kai Huang wrote:
If ENCLS VMEXIT is not present then we cannot support SGX virtualization.
This patch detects presence of ENCLS VMEXIT. A Xen boot boolean parameter
'sgx' is also added to manually
Hi Julien,
Thanks for pointing out. I'll move to x86 specific.
I've cc-ed all maintainers reported by ./scripts/get_maintainer.pl,
looks this script doesn't report all maintainers. Sorry. I'll add ARM
maintainers next time.
Thanks,
-Kai
On 7/12/2017 8:14 AM, Julien Grall wrote:
Hi,
On 07/
On 6/28/2016 8:37 PM, Jan Beulich wrote:
On 28.06.16 at 10:12, wrote:
From: Kai Huang
On the 24th I had asked you privately to please follow Xen patch
submission rules: Patches get sent _to_ the list, and maintainers
get _cc_-ed. People receiving mails may have rules in place in their
mail
Hi Kevin, Jan,
Thanks for comments.
On 6/24/2016 11:31 PM, Jan Beulich wrote:
On 24.06.16 at 12:56, wrote:
From: kaih.li...@gmail.com [mailto:kaih.li...@gmail.com]
Sent: Friday, June 24, 2016 6:45 PM
--- a/xen/include/asm-x86/msr-index.h
+++ b/xen/include/asm-x86/msr-index.h
@@ -133,12 +133,
On 6/22/2016 11:44 PM, Jan Beulich wrote:
On 22.06.16 at 12:17, wrote:
@@ -288,7 +289,6 @@
#define MSR_IA32_PLATFORM_ID 0x0017
#define MSR_IA32_EBL_CR_POWERON0x002a
#define MSR_IA32_EBC_FREQUENCY_ID 0x002c
-#define MSR_IA32_FEATURE_CONTROL 0
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